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dad30dd72b
Add support for updating FCB/DBBT on i.MX7: - additional new fields in FCB structure - Leverage hardware BCH/randomizer for writing FCB Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/*
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* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _IMX_NAND_BCB_H_
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#define _IMX_NAND_BCB_H_
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#define FCB_FINGERPRINT 0x20424346 /* 'FCB' */
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#define FCB_VERSION_1 0x01000000
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#define DBBT_FINGERPRINT2 0x54424244 /* 'DBBT' */
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#define DBBT_VERSION_1 0x01000000
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struct dbbt_block {
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u32 checksum; /* reserved on i.MX6 */
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u32 fingerprint;
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u32 version;
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u32 numberbb; /* reserved on i.MX6 */
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u32 dbbtpages;
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};
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struct fcb_block {
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u32 checksum; /* First fingerprint in first byte */
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u32 fingerprint; /* 2nd fingerprint at byte 4 */
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u32 version; /* 3rd fingerprint at byte 8 */
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u8 datasetup;
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u8 datahold;
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u8 addr_setup;
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u8 dsample_time;
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/* These are for application use only and not for ROM. */
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u8 nandtiming;
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u8 rea;
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u8 rloh;
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u8 rhoh;
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u32 pagesize; /* 2048 for 2K pages, 4096 for 4K pages */
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u32 oob_pagesize; /* 2112 for 2K pages, 4314 for 4K pages */
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u32 sectors; /* Number of 2K sections per block */
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u32 nr_nand; /* Total Number of NANDs - not used by ROM */
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u32 nr_die; /* Number of separate chips in this NAND */
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u32 celltype; /* MLC or SLC */
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u32 ecc_type; /* Type of ECC, can be one of BCH-0-20 */
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u32 ecc_nr; /* Number of bytes for Block0 - BCH */
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/* Block size in bytes for all blocks other than Block0 - BCH */
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u32 ecc_size;
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u32 ecc_level; /* Ecc level for Block 0 - BCH */
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u32 meta_size; /* Metadata size - BCH */
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/* Number of blocks per page for ROM use - BCH */
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u32 nr_blocks;
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u32 ecc_type_sdk; /* Type of ECC, can be one of BCH-0-20 */
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u32 ecc_nr_sdk; /* Number of bytes for Block0 - BCH */
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/* Block size in bytes for all blocks other than Block0 - BCH */
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u32 ecc_size_sdk;
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u32 ecc_level_sdk; /* Ecc level for Block 0 - BCH */
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/* Number of blocks per page for SDK use - BCH */
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u32 nr_blocks_sdk;
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u32 meta_size_sdk; /* Metadata size - BCH */
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u32 erase_th; /* To set into BCH_MODE register */
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/*
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* 0: normal boot
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* 1: to load patch starting next to FCB
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*/
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u32 bootpatch;
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u32 patch_size; /* Size of patch in sectors */
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u32 fw1_start; /* Firmware image starts on this sector */
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u32 fw2_start; /* Secondary FW Image starting Sector */
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u32 fw1_pages; /* Number of sectors in firmware image */
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u32 fw2_pages; /* Number of sector in secondary FW image */
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u32 dbbt_start; /* Page address where dbbt search area begins */
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/*
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* Byte in page data that have manufacturer marked bad block marker,
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* this will be swapped with metadata[0] to complete page data.
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*/
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u32 bb_byte;
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/*
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* For BCH ECC sizes other than 8 and 16 the bad block marker does not
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* start at 0th bit of bb_byte. This field is used to get to
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* the start bit of bad block marker byte with in bb_byte
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*/
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u32 bb_start_bit;
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/*
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* FCB value that gives byte offset for
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* bad block marker on physical NAND page
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*/
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u32 phy_offset;
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u32 bchtype;
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u32 readlatency;
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u32 predelay;
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u32 cedelay;
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u32 postdelay;
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u32 cmdaddpause;
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u32 datapause;
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u32 tmspeed;
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u32 busytimeout;
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/* the flag to enable (1)/disable(0) bi swap */
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u32 disbbm;
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/* The swap position of main area in spare area */
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u32 spare_offset;
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/* Actual for iMX7 only */
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u32 onfi_sync_enable;
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u32 onfi_sync_speed;
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u32 onfi_sync_nand_data;
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u32 reserved2[6];
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u32 disbbm_search;
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u32 disbbm_search_limit;
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u32 reserved3[15];
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u32 read_retry_enable;
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u32 reserved4[1];
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u32 fill_to_1024[183];
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};
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#endif /* _IMX_NAND_BCB_H_ */
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