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196 lines
7.2 KiB
C
196 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX_H
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#define __DT_BINDINGS_CLOCK_IMX_H
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/* LPCG clocks */
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/* LSIO SS LPCG */
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#define IMX_LSIO_LPCG_PWM0_IPG_CLK 0
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#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1
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#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2
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#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
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#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
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#define IMX_LSIO_LPCG_PWM1_IPG_CLK 5
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#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6
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#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7
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#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
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#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
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#define IMX_LSIO_LPCG_PWM2_IPG_CLK 10
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#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11
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#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12
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#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
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#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
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#define IMX_LSIO_LPCG_PWM3_IPG_CLK 15
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#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16
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#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17
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#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
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#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
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#define IMX_LSIO_LPCG_PWM4_IPG_CLK 20
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#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21
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#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22
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#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
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#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
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#define IMX_LSIO_LPCG_PWM5_IPG_CLK 25
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#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26
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#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27
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#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
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#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
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#define IMX_LSIO_LPCG_PWM6_IPG_CLK 30
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#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31
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#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32
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#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
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#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
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#define IMX_LSIO_LPCG_PWM7_IPG_CLK 35
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#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36
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#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37
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#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
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#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
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#define IMX_LSIO_LPCG_GPT0_IPG_CLK 40
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#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41
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#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42
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#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
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#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
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#define IMX_LSIO_LPCG_GPT1_IPG_CLK 45
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#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46
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#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47
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#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
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#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
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#define IMX_LSIO_LPCG_GPT2_IPG_CLK 50
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#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51
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#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52
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#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
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#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
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#define IMX_LSIO_LPCG_GPT3_IPG_CLK 55
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#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56
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#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57
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#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
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#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
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#define IMX_LSIO_LPCG_GPT4_IPG_CLK 60
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#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61
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#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62
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#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
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#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
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#define IMX_LSIO_LPCG_FSPI0_HCLK 65
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#define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66
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#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67
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#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68
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#define IMX_LSIO_LPCG_FSPI1_HCLK 69
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#define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70
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#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71
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#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72
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#define IMX_LSIO_LPCG_CLK_END 73
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/* Connectivity SS LPCG */
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#define IMX_CONN_LPCG_SDHC0_IPG_CLK 0
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#define IMX_CONN_LPCG_SDHC0_PER_CLK 1
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#define IMX_CONN_LPCG_SDHC0_HCLK 2
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#define IMX_CONN_LPCG_SDHC1_IPG_CLK 3
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#define IMX_CONN_LPCG_SDHC1_PER_CLK 4
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#define IMX_CONN_LPCG_SDHC1_HCLK 5
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#define IMX_CONN_LPCG_SDHC2_IPG_CLK 6
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#define IMX_CONN_LPCG_SDHC2_PER_CLK 7
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#define IMX_CONN_LPCG_SDHC2_HCLK 8
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#define IMX_CONN_LPCG_GPMI_APB_CLK 9
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#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10
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#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11
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#define IMX_CONN_LPCG_GPMI_BCH_CLK 12
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#define IMX_CONN_LPCG_APBHDMA_CLK 13
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#define IMX_CONN_LPCG_ENET0_ROOT_CLK 14
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#define IMX_CONN_LPCG_ENET0_TX_CLK 15
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#define IMX_CONN_LPCG_ENET0_AHB_CLK 16
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#define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17
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#define IMX_CONN_LPCG_ENET0_IPG_CLK 18
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#define IMX_CONN_LPCG_ENET1_ROOT_CLK 19
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#define IMX_CONN_LPCG_ENET1_TX_CLK 20
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#define IMX_CONN_LPCG_ENET1_AHB_CLK 21
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#define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22
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#define IMX_CONN_LPCG_ENET1_IPG_CLK 23
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#define IMX_CONN_LPCG_CLK_END 24
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/* ADMA SS LPCG */
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#define IMX_ADMA_LPCG_UART0_IPG_CLK 0
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#define IMX_ADMA_LPCG_UART0_BAUD_CLK 1
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#define IMX_ADMA_LPCG_UART1_IPG_CLK 2
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#define IMX_ADMA_LPCG_UART1_BAUD_CLK 3
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#define IMX_ADMA_LPCG_UART2_IPG_CLK 4
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#define IMX_ADMA_LPCG_UART2_BAUD_CLK 5
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#define IMX_ADMA_LPCG_UART3_IPG_CLK 6
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#define IMX_ADMA_LPCG_UART3_BAUD_CLK 7
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#define IMX_ADMA_LPCG_SPI0_IPG_CLK 8
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#define IMX_ADMA_LPCG_SPI1_IPG_CLK 9
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#define IMX_ADMA_LPCG_SPI2_IPG_CLK 10
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#define IMX_ADMA_LPCG_SPI3_IPG_CLK 11
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#define IMX_ADMA_LPCG_SPI0_CLK 12
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#define IMX_ADMA_LPCG_SPI1_CLK 13
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#define IMX_ADMA_LPCG_SPI2_CLK 14
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#define IMX_ADMA_LPCG_SPI3_CLK 15
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#define IMX_ADMA_LPCG_CAN0_IPG_CLK 16
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#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17
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#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
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#define IMX_ADMA_LPCG_CAN1_IPG_CLK 19
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#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20
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#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
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#define IMX_ADMA_LPCG_CAN2_IPG_CLK 22
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#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23
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#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
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#define IMX_ADMA_LPCG_I2C0_CLK 25
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#define IMX_ADMA_LPCG_I2C1_CLK 26
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#define IMX_ADMA_LPCG_I2C2_CLK 27
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#define IMX_ADMA_LPCG_I2C3_CLK 28
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#define IMX_ADMA_LPCG_I2C0_IPG_CLK 29
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#define IMX_ADMA_LPCG_I2C1_IPG_CLK 30
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#define IMX_ADMA_LPCG_I2C2_IPG_CLK 31
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#define IMX_ADMA_LPCG_I2C3_IPG_CLK 32
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#define IMX_ADMA_LPCG_FTM0_CLK 33
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#define IMX_ADMA_LPCG_FTM1_CLK 34
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#define IMX_ADMA_LPCG_FTM0_IPG_CLK 35
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#define IMX_ADMA_LPCG_FTM1_IPG_CLK 36
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#define IMX_ADMA_LPCG_PWM_HI_CLK 37
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#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
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#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
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#define IMX_ADMA_LPCG_LCD_APB_CLK 40
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#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
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#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
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#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
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#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
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#define IMX_ADMA_LPCG_CLK_END 45
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#define IMX_ADMA_ACM_AUD_CLK0_SEL 0
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#define IMX_ADMA_ACM_AUD_CLK1_SEL 1
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#define IMX_ADMA_ACM_MCLKOUT0_SEL 2
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#define IMX_ADMA_ACM_MCLKOUT1_SEL 3
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#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4
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#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5
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#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6
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#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7
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#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8
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#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9
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#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10
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#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11
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#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12
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#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13
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#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14
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#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15
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#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16
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#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17
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#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18
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#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19
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#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20
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#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21
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#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22
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#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23
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#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24
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#define IMX_ADMA_ACM_CLK_END 25
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#endif /* __DT_BINDINGS_CLOCK_IMX_H */
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