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189 lines
6.3 KiB
C
189 lines
6.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H
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/* GCC clocks */
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#define GPLL0 0
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#define GPLL0_OUT_AUX2 1
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#define GPLL1 2
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#define GPLL10 3
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#define GPLL11 4
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#define GPLL3 5
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#define GPLL3_OUT_MAIN 6
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#define GPLL4 7
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#define GPLL5 8
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#define GPLL6 9
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#define GPLL6_OUT_MAIN 10
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#define GPLL7 11
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#define GPLL8 12
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#define GPLL8_OUT_MAIN 13
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#define GPLL9 14
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#define GPLL9_OUT_MAIN 15
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#define GCC_AHB2PHY_CSI_CLK 16
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#define GCC_AHB2PHY_USB_CLK 17
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#define GCC_APC_VS_CLK 18
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#define GCC_BIMC_GPU_AXI_CLK 19
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#define GCC_BOOT_ROM_AHB_CLK 20
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#define GCC_CAM_THROTTLE_NRT_CLK 21
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#define GCC_CAM_THROTTLE_RT_CLK 22
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#define GCC_CAMERA_AHB_CLK 23
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#define GCC_CAMERA_XO_CLK 24
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#define GCC_CAMSS_AXI_CLK 25
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#define GCC_CAMSS_AXI_CLK_SRC 26
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#define GCC_CAMSS_CAMNOC_ATB_CLK 27
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#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 28
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#define GCC_CAMSS_CCI_0_CLK 29
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#define GCC_CAMSS_CCI_CLK_SRC 30
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#define GCC_CAMSS_CPHY_0_CLK 31
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#define GCC_CAMSS_CPHY_1_CLK 32
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 33
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#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 34
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 35
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#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 36
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#define GCC_CAMSS_MCLK0_CLK 37
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#define GCC_CAMSS_MCLK0_CLK_SRC 38
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#define GCC_CAMSS_MCLK1_CLK 39
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#define GCC_CAMSS_MCLK1_CLK_SRC 40
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#define GCC_CAMSS_MCLK2_CLK 41
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#define GCC_CAMSS_MCLK2_CLK_SRC 42
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#define GCC_CAMSS_MCLK3_CLK 43
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#define GCC_CAMSS_MCLK3_CLK_SRC 44
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#define GCC_CAMSS_NRT_AXI_CLK 45
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#define GCC_CAMSS_OPE_AHB_CLK 46
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#define GCC_CAMSS_OPE_AHB_CLK_SRC 47
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#define GCC_CAMSS_OPE_CLK 48
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#define GCC_CAMSS_OPE_CLK_SRC 49
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#define GCC_CAMSS_RT_AXI_CLK 50
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#define GCC_CAMSS_TFE_0_CLK 51
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#define GCC_CAMSS_TFE_0_CLK_SRC 52
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#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 53
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#define GCC_CAMSS_TFE_0_CSID_CLK 54
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#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 55
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#define GCC_CAMSS_TFE_1_CLK 56
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#define GCC_CAMSS_TFE_1_CLK_SRC 57
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#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 58
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#define GCC_CAMSS_TFE_1_CSID_CLK 59
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#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 60
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#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 61
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#define GCC_CAMSS_TOP_AHB_CLK 62
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#define GCC_CAMSS_TOP_AHB_CLK_SRC 63
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 64
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#define GCC_CPUSS_AHB_CLK 65
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#define GCC_CPUSS_AHB_CLK_SRC 66
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 67
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#define GCC_CPUSS_GNOC_CLK 68
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#define GCC_CPUSS_THROTTLE_CORE_CLK 69
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#define GCC_CPUSS_THROTTLE_XO_CLK 70
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#define GCC_DISP_AHB_CLK 71
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#define GCC_DISP_GPLL0_CLK_SRC 72
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 73
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#define GCC_DISP_HF_AXI_CLK 74
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#define GCC_DISP_THROTTLE_CORE_CLK 75
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#define GCC_DISP_XO_CLK 76
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#define GCC_GP1_CLK 77
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#define GCC_GP1_CLK_SRC 78
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#define GCC_GP2_CLK 79
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#define GCC_GP2_CLK_SRC 80
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#define GCC_GP3_CLK 81
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#define GCC_GP3_CLK_SRC 82
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#define GCC_GPU_CFG_AHB_CLK 83
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#define GCC_GPU_GPLL0_CLK_SRC 84
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 85
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#define GCC_GPU_IREF_CLK 86
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#define GCC_GPU_MEMNOC_GFX_CLK 87
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#define GCC_GPU_SNOC_DVM_GFX_CLK 88
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#define GCC_GPU_THROTTLE_CORE_CLK 89
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#define GCC_GPU_THROTTLE_XO_CLK 90
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#define GCC_PDM2_CLK 91
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#define GCC_PDM2_CLK_SRC 92
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#define GCC_PDM_AHB_CLK 93
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#define GCC_PDM_XO4_CLK 94
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#define GCC_PWM0_XO512_CLK 95
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 96
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 97
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#define GCC_QMIP_CPUSS_CFG_AHB_CLK 98
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#define GCC_QMIP_DISP_AHB_CLK 99
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#define GCC_QMIP_GPU_CFG_AHB_CLK 100
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 101
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 102
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#define GCC_QUPV3_WRAP0_CORE_CLK 103
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#define GCC_QUPV3_WRAP0_S0_CLK 104
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 105
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#define GCC_QUPV3_WRAP0_S1_CLK 106
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 107
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#define GCC_QUPV3_WRAP0_S2_CLK 108
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 109
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#define GCC_QUPV3_WRAP0_S3_CLK 110
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 111
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#define GCC_QUPV3_WRAP0_S4_CLK 112
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 113
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#define GCC_QUPV3_WRAP0_S5_CLK 114
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 115
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 116
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 117
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#define GCC_SDCC1_AHB_CLK 118
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#define GCC_SDCC1_APPS_CLK 119
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#define GCC_SDCC1_APPS_CLK_SRC 120
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#define GCC_SDCC1_ICE_CORE_CLK 121
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 122
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#define GCC_SDCC2_AHB_CLK 123
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#define GCC_SDCC2_APPS_CLK 124
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#define GCC_SDCC2_APPS_CLK_SRC 125
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 126
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#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 127
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#define GCC_USB30_PRIM_MASTER_CLK 128
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 129
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV 132
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#define GCC_USB30_PRIM_SLEEP_CLK 133
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#define GCC_USB3_PRIM_CLKREF_CLK 134
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 137
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#define GCC_VCODEC0_AXI_CLK 138
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#define GCC_VENUS_AHB_CLK 139
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#define GCC_VENUS_CTL_AXI_CLK 140
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#define GCC_VIDEO_AHB_CLK 141
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#define GCC_VIDEO_AXI0_CLK 142
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#define GCC_VIDEO_THROTTLE_CORE_CLK 143
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#define GCC_VIDEO_VCODEC0_SYS_CLK 144
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#define GCC_VIDEO_VENUS_CLK_SRC 145
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#define GCC_VIDEO_VENUS_CTL_CLK 146
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#define GCC_VIDEO_XO_CLK 147
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/* GCC resets */
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#define GCC_CAMSS_OPE_BCR 0
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#define GCC_CAMSS_TFE_BCR 1
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#define GCC_CAMSS_TOP_BCR 2
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#define GCC_GPU_BCR 3
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#define GCC_MMSS_BCR 4
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#define GCC_PDM_BCR 5
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#define GCC_QUPV3_WRAPPER_0_BCR 6
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#define GCC_SDCC1_BCR 7
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#define GCC_SDCC2_BCR 8
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#define GCC_USB30_PRIM_BCR 9
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
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#define GCC_VCODEC0_BCR 11
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#define GCC_VENUS_BCR 12
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#define GCC_VIDEO_INTERFACE_BCR 13
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#define GCC_QUSB2PHY_PRIM_BCR 14
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#define GCC_USB3_PHY_PRIM_SP0_BCR 15
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#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 16
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/* Indexes for GDSCs */
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#define GCC_CAMSS_TOP_GDSC 0
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#define GCC_USB30_PRIM_GDSC 1
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#define GCC_VCODEC0_GDSC 2
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#define GCC_VENUS_GDSC 3
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#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 4
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#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 5
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#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6
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#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 7
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#endif
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