mirror of
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224 lines
7.6 KiB
C
224 lines
7.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018-2023 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
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#define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
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#define GPLL0_MAIN 0
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#define GPLL0 1
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#define GPLL2_MAIN 2
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#define GPLL2 3
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#define GPLL4_MAIN 4
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#define GPLL4 5
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#define GCC_SLEEP_CLK_SRC 6
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#define APSS_AHB_CLK_SRC 7
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#define APSS_AXI_CLK_SRC 8
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 15
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 16
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 17
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 18
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 19
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 20
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#define BLSP1_UART1_APPS_CLK_SRC 21
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#define BLSP1_UART2_APPS_CLK_SRC 22
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#define BLSP1_UART3_APPS_CLK_SRC 23
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#define BLSP1_UART4_APPS_CLK_SRC 24
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#define BLSP1_UART5_APPS_CLK_SRC 25
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#define BLSP1_UART6_APPS_CLK_SRC 26
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#define GCC_APSS_AHB_CLK 27
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#define GCC_APSS_AXI_CLK 28
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 37
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 38
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 39
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 40
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#define GCC_BLSP1_UART1_APPS_CLK 41
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#define GCC_BLSP1_UART2_APPS_CLK 42
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#define GCC_BLSP1_UART3_APPS_CLK 43
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#define GCC_BLSP1_UART4_APPS_CLK 44
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#define GCC_BLSP1_UART5_APPS_CLK 45
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#define GCC_BLSP1_UART6_APPS_CLK 46
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#define PCIE0_AXI_M_CLK_SRC 47
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#define GCC_PCIE0_AXI_M_CLK 48
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#define PCIE1_AXI_M_CLK_SRC 49
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#define GCC_PCIE1_AXI_M_CLK 50
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#define PCIE2_AXI_M_CLK_SRC 51
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#define GCC_PCIE2_AXI_M_CLK 52
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#define PCIE3_AXI_M_CLK_SRC 53
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#define GCC_PCIE3_AXI_M_CLK 54
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#define PCIE0_AXI_S_CLK_SRC 55
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 56
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#define GCC_PCIE0_AXI_S_CLK 57
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#define PCIE1_AXI_S_CLK_SRC 58
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#define GCC_PCIE1_AXI_S_BRIDGE_CLK 59
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#define GCC_PCIE1_AXI_S_CLK 60
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#define PCIE2_AXI_S_CLK_SRC 61
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#define GCC_PCIE2_AXI_S_BRIDGE_CLK 62
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#define GCC_PCIE2_AXI_S_CLK 63
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#define PCIE3_AXI_S_CLK_SRC 64
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#define GCC_PCIE3_AXI_S_BRIDGE_CLK 65
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#define GCC_PCIE3_AXI_S_CLK 66
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#define PCIE0_PIPE_CLK_SRC 67
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#define PCIE1_PIPE_CLK_SRC 68
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#define PCIE2_PIPE_CLK_SRC 69
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#define PCIE3_PIPE_CLK_SRC 70
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#define PCIE_AUX_CLK_SRC 71
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#define GCC_PCIE0_AUX_CLK 72
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#define GCC_PCIE1_AUX_CLK 73
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#define GCC_PCIE2_AUX_CLK 74
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#define GCC_PCIE3_AUX_CLK 75
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#define PCIE0_RCHNG_CLK_SRC 76
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#define GCC_PCIE0_RCHNG_CLK 77
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#define PCIE1_RCHNG_CLK_SRC 78
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#define GCC_PCIE1_RCHNG_CLK 79
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#define PCIE2_RCHNG_CLK_SRC 80
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#define GCC_PCIE2_RCHNG_CLK 81
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#define PCIE3_RCHNG_CLK_SRC 82
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#define GCC_PCIE3_RCHNG_CLK 83
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#define GCC_PCIE0_AHB_CLK 84
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#define GCC_PCIE1_AHB_CLK 85
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#define GCC_PCIE2_AHB_CLK 86
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#define GCC_PCIE3_AHB_CLK 87
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#define USB0_AUX_CLK_SRC 88
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#define GCC_USB0_AUX_CLK 89
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#define USB0_MASTER_CLK_SRC 90
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#define GCC_USB0_MASTER_CLK 91
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#define GCC_SNOC_USB_CLK 92
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#define GCC_ANOC_USB_AXI_CLK 93
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#define USB0_MOCK_UTMI_CLK_SRC 94
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#define USB0_MOCK_UTMI_DIV_CLK_SRC 95
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#define GCC_USB0_MOCK_UTMI_CLK 96
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#define USB0_PIPE_CLK_SRC 97
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#define GCC_USB0_PHY_CFG_AHB_CLK 98
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#define SDCC1_APPS_CLK_SRC 99
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#define GCC_SDCC1_APPS_CLK 100
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#define SDCC1_ICE_CORE_CLK_SRC 101
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#define GCC_SDCC1_ICE_CORE_CLK 102
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#define GCC_SDCC1_AHB_CLK 103
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#define PCNOC_BFDCD_CLK_SRC 104
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#define GCC_NSSCFG_CLK 105
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#define GCC_NSSNOC_NSSCC_CLK 106
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#define GCC_NSSCC_CLK 107
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#define GCC_NSSNOC_PCNOC_1_CLK 108
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#define GCC_QDSS_DAP_AHB_CLK 109
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#define GCC_QDSS_CFG_AHB_CLK 110
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#define GCC_QPIC_AHB_CLK 111
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#define GCC_QPIC_CLK 112
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#define GCC_BLSP1_AHB_CLK 113
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#define GCC_MDIO_AHB_CLK 114
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#define GCC_PRNG_AHB_CLK 115
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#define GCC_UNIPHY0_AHB_CLK 116
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#define GCC_UNIPHY1_AHB_CLK 117
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#define GCC_UNIPHY2_AHB_CLK 118
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#define GCC_CMN_12GPLL_AHB_CLK 119
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#define GCC_CMN_12GPLL_APU_CLK 120
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#define SYSTEM_NOC_BFDCD_CLK_SRC 121
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#define GCC_NSSNOC_SNOC_CLK 122
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#define GCC_NSSNOC_SNOC_1_CLK 123
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#define GCC_QDSS_ETR_USB_CLK 124
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#define WCSS_AHB_CLK_SRC 125
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#define GCC_Q6_AHB_CLK 126
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#define GCC_Q6_AHB_S_CLK 127
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#define GCC_WCSS_ECAHB_CLK 128
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#define GCC_WCSS_ACMT_CLK 129
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#define GCC_SYS_NOC_WCSS_AHB_CLK 130
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#define WCSS_AXI_M_CLK_SRC 131
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#define GCC_ANOC_WCSS_AXI_M_CLK 132
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#define QDSS_AT_CLK_SRC 133
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#define GCC_Q6SS_ATBM_CLK 134
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#define GCC_WCSS_DBG_IFC_ATB_CLK 135
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#define GCC_NSSNOC_ATB_CLK 136
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#define GCC_QDSS_AT_CLK 137
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#define GCC_SYS_NOC_AT_CLK 138
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#define GCC_PCNOC_AT_CLK 139
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#define GCC_USB0_EUD_AT_CLK 140
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#define GCC_QDSS_EUD_AT_CLK 141
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#define QDSS_STM_CLK_SRC 142
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#define GCC_QDSS_STM_CLK 143
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#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144
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#define QDSS_TRACECLKIN_CLK_SRC 145
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#define GCC_QDSS_TRACECLKIN_CLK 146
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#define QDSS_TSCTR_CLK_SRC 147
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#define GCC_Q6_TSCTR_1TO2_CLK 148
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#define GCC_WCSS_DBG_IFC_NTS_CLK 149
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#define GCC_QDSS_TSCTR_DIV2_CLK 150
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#define GCC_QDSS_TS_CLK 151
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#define GCC_QDSS_TSCTR_DIV4_CLK 152
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#define GCC_NSS_TS_CLK 153
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#define GCC_QDSS_TSCTR_DIV8_CLK 154
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#define GCC_QDSS_TSCTR_DIV16_CLK 155
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#define GCC_Q6SS_PCLKDBG_CLK 156
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#define GCC_Q6SS_TRIG_CLK 157
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#define GCC_WCSS_DBG_IFC_APB_CLK 158
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#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159
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#define GCC_QDSS_DAP_CLK 160
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#define GCC_QDSS_APB2JTAG_CLK 161
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#define GCC_QDSS_TSCTR_DIV3_CLK 162
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#define QPIC_IO_MACRO_CLK_SRC 163
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#define GCC_QPIC_IO_MACRO_CLK 164
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#define Q6_AXI_CLK_SRC 165
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#define GCC_Q6_AXIM_CLK 166
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#define GCC_WCSS_Q6_TBU_CLK 167
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#define GCC_MEM_NOC_Q6_AXI_CLK 168
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#define Q6_AXIM2_CLK_SRC 169
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#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170
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#define GCC_NSSNOC_MEMNOC_CLK 171
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#define GCC_NSSNOC_MEM_NOC_1_CLK 172
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#define GCC_NSS_TBU_CLK 173
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#define GCC_MEM_NOC_NSSNOC_CLK 174
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#define LPASS_AXIM_CLK_SRC 175
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#define LPASS_SWAY_CLK_SRC 176
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#define ADSS_PWM_CLK_SRC 177
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#define GCC_ADSS_PWM_CLK 178
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#define GP1_CLK_SRC 179
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#define GP2_CLK_SRC 180
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#define GP3_CLK_SRC 181
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#define DDRSS_SMS_SLOW_CLK_SRC 182
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#define GCC_XO_CLK_SRC 183
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#define GCC_XO_CLK 184
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#define GCC_NSSNOC_QOSGEN_REF_CLK 185
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 186
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#define GCC_XO_DIV4_CLK 187
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#define GCC_UNIPHY0_SYS_CLK 188
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#define GCC_UNIPHY1_SYS_CLK 189
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#define GCC_UNIPHY2_SYS_CLK 190
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#define GCC_CMN_12GPLL_SYS_CLK 191
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#define GCC_NSSNOC_XO_DCD_CLK 192
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#define GCC_Q6SS_BOOT_CLK 193
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#define UNIPHY_SYS_CLK_SRC 194
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#define NSS_TS_CLK_SRC 195
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#define GCC_ANOC_PCIE0_1LANE_M_CLK 196
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#define GCC_ANOC_PCIE1_1LANE_M_CLK 197
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#define GCC_ANOC_PCIE2_2LANE_M_CLK 198
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#define GCC_ANOC_PCIE3_2LANE_M_CLK 199
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#define GCC_SNOC_PCIE0_1LANE_S_CLK 200
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#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
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#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
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#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
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#define GCC_CRYPTO_CLK_SRC 204
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#define GCC_CRYPTO_CLK 205
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#define GCC_CRYPTO_AXI_CLK 206
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#define GCC_CRYPTO_AHB_CLK 207
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#define GCC_USB0_PIPE_CLK 208
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#define GCC_USB0_SLEEP_CLK 209
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#define GCC_PCIE0_PIPE_CLK 210
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#define GCC_PCIE1_PIPE_CLK 211
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#define GCC_PCIE2_PIPE_CLK 212
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#define GCC_PCIE3_PIPE_CLK 213
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#endif
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