Stephen Warren 790f7719e2 ARM: tegra: pinmux: account for different drivegroup base registers ...

Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

2015-03-04 10:09:01 -07:00

..

clock-tables.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

clock.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

flow.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

funcmux.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

gp_padctrl.h

Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table

2013-03-25 09:56:07 -07:00

gpio.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

hardware.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

mc.h

ARM: tegra: Use mem size from MC in combination with get_ram_size()

2014-10-22 09:30:55 -07:00

pinmux.h

ARM: tegra: pinmux: account for different drivegroup base registers

2015-03-04 10:09:01 -07:00

pmu.h

Tegra114: Add arch-tegra114 include files

2013-02-11 10:35:25 -07:00

powergate.h

ARM: tegra: Implement powergate support

2014-12-18 13:19:20 -07:00

sysctr.h

Tegra114: Initialize System Counter (TSC) with osc frequency

2013-04-15 11:01:38 -07:00

tegra.h

ARM: tegra: Use mem size from MC in combination with get_ram_size()

2014-10-22 09:30:55 -07:00