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9d24274509
Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
93 lines
1.8 KiB
C
93 lines
1.8 KiB
C
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/microblaze_timer.h>
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#include <asm/microblaze_intc.h>
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volatile int timestamp = 0;
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microblaze_timer_t *tmr;
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ulong get_timer (ulong base)
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{
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if (tmr)
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return timestamp - base;
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return timestamp++ - base;
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}
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void __udelay(unsigned long usec)
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{
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u32 i;
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if (tmr) {
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i = get_timer(0);
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while ((get_timer(0) - i) < (usec / 1000))
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;
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} else {
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for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++)
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;
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}
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}
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#ifndef CONFIG_SPL_BUILD
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static void timer_isr(void *arg)
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{
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timestamp++;
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tmr->control = tmr->control | TIMER_INTERRUPT;
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}
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int timer_init (void)
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{
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int irq = -1;
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u32 preload = 0;
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u32 ret = 0;
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#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
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preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
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irq = CONFIG_SYS_TIMER_0_IRQ;
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tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
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#endif
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if (tmr && preload && irq >= 0) {
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tmr->loadreg = preload;
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tmr->control = TIMER_INTERRUPT | TIMER_RESET;
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tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\
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TIMER_RELOAD | TIMER_DOWN_COUNT;
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timestamp = 0;
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ret = install_interrupt_handler (irq, timer_isr, (void *)tmr);
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if (ret)
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tmr = NULL;
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}
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/* No problem if timer is not found/initialized */
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return 0;
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}
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#else
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int timer_init(void)
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{
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return 0;
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}
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#endif
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On Microblaze it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On Microblaze it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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