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40f8dec54d
Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
25 lines
465 B
ArmAsm
25 lines
465 B
ArmAsm
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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ENTRY(armv8_switch_to_el2)
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switch_el x0, 1f, 0f, 0f
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0: ret
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1: armv8_switch_to_el2_m x0
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ENDPROC(armv8_switch_to_el2)
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ENTRY(armv8_switch_to_el1)
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switch_el x0, 0f, 1f, 0f
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0: ret
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1: armv8_switch_to_el1_m x0, x1
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ENDPROC(armv8_switch_to_el1)
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