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	Add support for the Comvetia i.MX6Q LXR2 board, which is uses the Phytec PFLA02 SoM. Based on the original work from Stefano Babic <sbabic@denx.de>. The Phytec PFLA02 devicetrees are taken from kernel 6.11-rc7. The imx6q-lxr.dts has been submitted upstream: https://lore.kernel.org/linux-devicetree/20240913200906.1753458-3-festevam@gmail.com/ After it gets accepted in mainline (most likely in kernel 6.13), the lxr2 board can then be switched to OF_UPSTREAM and these device trees can be removed from U-Boot. Signed-off-by: Fabio Estevam <festevam@denx.de>
		
			
				
	
	
		
			88 lines
		
	
	
		
			1.5 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			88 lines
		
	
	
		
			1.5 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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| //
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| // Copyright 2024 Comvetia AG
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| 
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| /dts-v1/;
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| #include "imx6q-phytec-pfla02.dtsi"
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| 
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| / {
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| 	model = "COMVETIA QSoIP LXR-2";
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| 	compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
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| 
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| 	chosen {
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| 		stdout-path = &uart4;
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| 	};
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| 
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| 	spi {
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| 		compatible = "spi-gpio";
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| 		pinctrl-names = "default";
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| 		pinctrl-0 = <&pinctrl_spi_gpio>;
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| 		sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
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| 		mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
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| 		num-chipselects = <0>;
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		fpga@0 {
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| 			compatible = "altr,fpga-passive-serial";
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| 			reg = <0>;
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| 			pinctrl-names = "default";
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| 			pinctrl-0 = <&pinctrl_fpga>;
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| 			nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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| 			nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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| 			confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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| 		};
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| 	};
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| };
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| 
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| &ecspi3 {
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&pinctrl_ecspi3>;
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| 	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
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| 	status = "okay";
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| 
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| 	flash@0 {
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| 		compatible = "jedec,spi-nor";
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| 		reg = <0>;
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| 		spi-max-frequency = <20000000>;
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| 	};
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| };
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| 
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| &fec {
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| 	status = "okay";
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| };
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| 
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| &i2c3 {
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| 	status = "okay";
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| };
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| 
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| &uart3 {
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| 	status = "okay";
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| };
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| 
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| &uart4 {
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| 	status = "okay";
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| };
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| 
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| &usdhc3 {
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| 	no-1-8-v;
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| 	status = "okay";
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| };
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| 
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| &iomuxc {
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| 	pinctrl_fpga: fpgagrp {
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| 		fsl,pins = <
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| 			MX6QDL_PAD_GPIO_6__GPIO1_IO06       0x1b0b0
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| 			MX6QDL_PAD_DI0_PIN2__GPIO4_IO18     0x1b0b0
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| 			MX6QDL_PAD_DI0_PIN3__GPIO4_IO19     0x1b0b0
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| 		>;
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| 	};
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| 
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| 	pinctrl_spi_gpio: spigpiogrp {
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| 		fsl,pins = <
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| 			MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08  0x1b0b0
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| 			MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07  0x1b0b0
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| 		>;
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| 	};
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| };
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