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https://github.com/smaeul/u-boot.git
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777544085d
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
78 lines
2.1 KiB
ArmAsm
78 lines
2.1 KiB
ArmAsm
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <version.h>
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/* Save the parameter pass in by previous boot loader */
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.global save_boot_params
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save_boot_params:
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/* save the parameter here */
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/*
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* Setup stack for exception, which is located
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* at the end of on-chip RAM. We don't expect exception prior to
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* relocation and if that happens, we won't worry -- it will overide
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* global data region as the code will goto reset. After relocation,
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* this region won't be used by other part of program.
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* Hence it is safe.
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*/
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ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
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ldr r1, =IRQ_STACK_START_IN
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str r0, [r1]
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bx lr
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/* Set up the platform, once the cpu has been initialized */
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.globl lowlevel_init
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lowlevel_init:
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/* Remap */
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#ifdef CONFIG_SPL_BUILD
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/*
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* SPL : configure the remap (L3 NIC-301 GPV)
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* so the on-chip RAM at lower memory instead ROM.
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*/
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ldr r0, =SOCFPGA_L3REGS_ADDRESS
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mov r1, #0x19
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str r1, [r0]
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#else
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/*
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* U-Boot : configure the remap (L3 NIC-301 GPV)
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* so the SDRAM at lower memory instead on-chip RAM.
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*/
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ldr r0, =SOCFPGA_L3REGS_ADDRESS
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mov r1, #0x2
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str r1, [r0]
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/* Private components security */
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/*
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* U-Boot : configure private timer, global timer and cpu
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* component access as non secure for kernel stage (as required
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* by kernel)
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*/
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mrc p15,4,r0,c15,c0,0
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add r1, r0, #0x54
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ldr r2, [r1]
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orr r2, r2, #0xff
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orr r2, r2, #0xf00
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str r2, [r1]
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#endif /* #ifdef CONFIG_SPL_BUILD */
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mov pc, lr
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