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1bf43b829e
This patch adds SPI driver for EXYNOS. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: jy0922.shim@samsung.com Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Padmavathi Venna <padma.v@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#ifndef __ASSEMBLY__
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/* SPI peripheral register map; padded to 64KB */
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struct exynos_spi {
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unsigned int ch_cfg; /* 0x00 */
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unsigned char reserved0[4];
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unsigned int mode_cfg; /* 0x08 */
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unsigned int cs_reg; /* 0x0c */
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unsigned char reserved1[4];
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unsigned int spi_sts; /* 0x14 */
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unsigned int tx_data; /* 0x18 */
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unsigned int rx_data; /* 0x1c */
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unsigned int pkt_cnt; /* 0x20 */
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unsigned char reserved2[4];
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unsigned char reserved3[4];
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unsigned int fb_clk; /* 0x2c */
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unsigned char padding[0xffd0];
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};
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#define EXYNOS_SPI_MAX_FREQ 50000000
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#define SPI_TIMEOUT_MS 10
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/* SPI_CHCFG */
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#define SPI_CH_HS_EN (1 << 6)
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#define SPI_CH_RST (1 << 5)
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#define SPI_SLAVE_MODE (1 << 4)
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#define SPI_CH_CPOL_L (1 << 3)
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#define SPI_CH_CPHA_B (1 << 2)
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#define SPI_RX_CH_ON (1 << 1)
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#define SPI_TX_CH_ON (1 << 0)
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/* SPI_MODECFG */
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#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
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#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
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/* SPI_CSREG */
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#define SPI_SLAVE_SIG_INACT (1 << 0)
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/* SPI_STS */
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#define SPI_ST_TX_DONE (1 << 25)
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#define SPI_FIFO_LVL_MASK 0x1ff
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#define SPI_TX_LVL_OFFSET 6
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#define SPI_RX_LVL_OFFSET 15
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/* Feedback Delay */
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#define SPI_CLK_BYPASS (0 << 0)
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#define SPI_FB_DELAY_90 (1 << 0)
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#define SPI_FB_DELAY_180 (2 << 0)
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#define SPI_FB_DELAY_270 (3 << 0)
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/* Packet Count */
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#define SPI_PACKET_CNT_EN (1 << 16)
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#endif /* __ASSEMBLY__ */
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#endif
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