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https://github.com/smaeul/u-boot.git
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150c24936b
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
107 lines
3.8 KiB
C
107 lines
3.8 KiB
C
/*
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* (C) Copyright 2010-2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/types.h>
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/* Stabilization delays, in usec */
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#define PLL_STABILIZATION_DELAY (300)
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#define IO_STABILIZATION_DELAY (1000)
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#define NVBL_PLLP_KHZ (216000)
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#define PLLX_ENABLED (1 << 30)
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#define CCLK_BURST_POLICY 0x20008888
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#define SUPER_CCLK_DIVIDER 0x80000000
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/* Calculate clock fractional divider value from ref and target frequencies */
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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/* Calculate clock frequency value from reference and clock divider value */
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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/* AVP/CPU ID */
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
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#define PG_UP_TAG_0 0x0
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#define CORESIGHT_UNLOCK 0xC5ACCE55;
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/* AP20-Specific Base Addresses */
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/* AP20 Base physical address of SDRAM. */
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#define AP20_BASE_PA_SDRAM 0x00000000
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/* AP20 Base physical address of internal SRAM. */
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#define AP20_BASE_PA_SRAM 0x40000000
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/* AP20 Size of internal SRAM (256KB). */
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#define AP20_BASE_PA_SRAM_SIZE 0x00040000
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/* AP20 Base physical address of flash. */
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#define AP20_BASE_PA_NOR_FLASH 0xD0000000
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/* AP20 Base physical address of boot information table. */
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#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
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/*
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* Super-temporary stacks for EXTREMELY early startup. The values chosen for
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* these addresses must be valid on ALL SOCs because this value is used before
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* we are able to differentiate between the SOC types.
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*
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* NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
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* stack is placed below the AVP stack. Once the CPU stack has been moved,
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* the AVP is free to use the IRAM the CPU stack previously occupied if
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* it should need to do so.
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*
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* NOTE: In multi-processor CPU complex configurations, each processor will have
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* its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
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* limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
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* stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
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* CPU.
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*/
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/* Common AVP early boot stack limit */
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#define AVP_EARLY_BOOT_STACK_LIMIT \
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(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
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/* Common AVP early boot stack size */
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#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
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/* Common CPU early boot stack limit */
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#define CPU_EARLY_BOOT_STACK_LIMIT \
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(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
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/* Common CPU early boot stack size */
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#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
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#define FLOW_MODE_STOP 2
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#define HALT_COP_EVENT_JTAG (1 << 28)
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#define HALT_COP_EVENT_IRQ_1 (1 << 11)
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#define HALT_COP_EVENT_FIQ_1 (1 << 9)
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/* This is the main entry into U-Boot, used by the Cortex-A9 */
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extern void _start(void);
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/**
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* Works out the SOC type used for clocks settings
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*
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* @return SOC type - see TEGRA_SOC...
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*/
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int tegra_get_chip_type(void);
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