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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
379 lines
7.3 KiB
ArmAsm
379 lines
7.3 KiB
ArmAsm
#include <config.h>
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#include <mpc86xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#ifndef CACHE_LINE_SIZE
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# define CACHE_LINE_SIZE L1_CACHE_BYTES
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#endif
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#if CACHE_LINE_SIZE == 128
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#define LG_CACHE_LINE_SIZE 7
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#elif CACHE_LINE_SIZE == 32
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#define LG_CACHE_LINE_SIZE 5
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#elif CACHE_LINE_SIZE == 16
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#define LG_CACHE_LINE_SIZE 4
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#elif CACHE_LINE_SIZE == 8
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#define LG_CACHE_LINE_SIZE 3
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#else
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# error "Invalid cache line size!"
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#endif
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/*
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* Most of this code is taken from 74xx_7xx/cache.S
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* and then cleaned up a bit
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*/
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/*
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* Invalidate L1 instruction cache.
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*/
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_GLOBAL(invalidate_l1_instruction_cache)
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/* use invalidate-all bit in HID0 */
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mfspr r3,HID0
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ori r3,r3,HID0_ICFI
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mtspr HID0,r3
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isync
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blr
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/*
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* Invalidate L1 data cache.
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*/
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_GLOBAL(invalidate_l1_data_cache)
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mfspr r3,HID0
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ori r3,r3,HID0_DCFI
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mtspr HID0,r3
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isync
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blr
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/*
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* Flush data cache.
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*/
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_GLOBAL(flush_dcache)
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lis r3,0
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lis r5,CACHE_LINE_SIZE
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flush:
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cmp 0,1,r3,r5
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bge done
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lwz r5,0(r3)
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lis r5,CACHE_LINE_SIZE
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addi r3,r3,0x4
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b flush
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done:
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blr
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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* This is a no-op on the 601.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_icache_range)
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li r5,CACHE_LINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,LG_CACHE_LINE_SIZE
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,CACHE_LINE_SIZE
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bdnz 2b
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sync /* additional sync needed on g4 */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*
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* clean_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(clean_dcache_range)
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li r5,CACHE_LINE_SIZE-1
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andc r3,r3,r5 /* align r3 down to cache line */
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subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
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add r4,r4,r5 /* r4 += cache_line_size-1 */
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srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
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beqlr /* if r4 == 0 return */
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mtctr r4 /* ctr = r4 */
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sync
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1: dcbst 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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li r5,CACHE_LINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,LG_CACHE_LINE_SIZE
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beqlr
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mtctr r4
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sync
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1: dcbf 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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sync /* wait for dcbf's to get to ram */
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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li r5,CACHE_LINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,LG_CACHE_LINE_SIZE
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beqlr
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mtctr r4
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sync
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1: dcbi 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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blr
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* void __flush_page_to_ram(void *page)
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*/
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_GLOBAL(__flush_page_to_ram)
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rlwinm r3,r3,0,0,19 /* Get page base address */
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li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 0b
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sync
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mtctr r4
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1: icbi 0,r6
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addi r6,r6,CACHE_LINE_SIZE
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bdnz 1b
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sync
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isync
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blr
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/*
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* Flush a particular page from the instruction cache.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* void __flush_icache_page(void *page)
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*/
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_GLOBAL(__flush_icache_page)
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li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
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mtctr r4
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1: icbi 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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sync
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isync
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blr
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/*
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* Clear a page using the dcbz instruction, which doesn't cause any
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* memory traffic (except to write out any cache lines which get
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* displaced). This only works on cacheable memory.
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*/
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_GLOBAL(clear_page)
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li r0,4096/CACHE_LINE_SIZE
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mtctr r0
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1: dcbz 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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blr
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/*
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* Enable L1 Instruction cache
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*/
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_GLOBAL(icache_enable)
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mfspr r3, HID0
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li r5, HID0_ICFI|HID0_ILOCK
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andc r3, r3, r5
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ori r3, r3, HID0_ICE
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ori r5, r3, HID0_ICFI
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mtspr HID0, r5
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mtspr HID0, r3
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isync
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blr
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/*
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* Disable L1 Instruction cache
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*/
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_GLOBAL(icache_disable)
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mflr r4
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bl invalidate_l1_instruction_cache /* uses r3 */
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sync
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mtlr r4
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mfspr r3, HID0
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li r5, 0
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ori r5, r5, HID0_ICE
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andc r3, r3, r5
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mtspr HID0, r3
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isync
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blr
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/*
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* Is instruction cache enabled?
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*/
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_GLOBAL(icache_status)
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mfspr r3, HID0
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andi. r3, r3, HID0_ICE
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blr
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_GLOBAL(l1dcache_enable)
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mfspr r3, HID0
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li r5, HID0_DCFI|HID0_DLOCK
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andc r3, r3, r5
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mtspr HID0, r3 /* no invalidate, unlock */
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ori r3, r3, HID0_DCE
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ori r5, r3, HID0_DCFI
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mtspr HID0, r5 /* enable + invalidate */
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mtspr HID0, r3 /* enable */
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sync
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blr
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/*
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* Enable data cache(s) - L1 and optionally L2
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* Calls l2cache_enable. LR saved in r5
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*/
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_GLOBAL(dcache_enable)
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mfspr r3, HID0
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li r5, HID0_DCFI|HID0_DLOCK
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andc r3, r3, r5
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mtspr HID0, r3 /* no invalidate, unlock */
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ori r3, r3, HID0_DCE
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ori r5, r3, HID0_DCFI
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mtspr HID0, r5 /* enable + invalidate */
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mtspr HID0, r3 /* enable */
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sync
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#ifdef CONFIG_SYS_L2
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mflr r5
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bl l2cache_enable /* uses r3 and r4 */
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sync
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mtlr r5
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#endif
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blr
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/*
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* Disable data cache(s) - L1 and optionally L2
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* Calls flush_dcache and l2cache_disable_no_flush.
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* LR saved in r4
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*/
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_GLOBAL(dcache_disable)
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mflr r4 /* save link register */
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bl flush_dcache /* uses r3 and r5 */
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sync
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mfspr r3, HID0
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li r5, HID0_DCFI|HID0_DLOCK
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andc r3, r3, r5
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mtspr HID0, r3 /* no invalidate, unlock */
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li r5, HID0_DCE|HID0_DCFI
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andc r3, r3, r5 /* no enable, no invalidate */
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mtspr HID0, r3
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sync
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#ifdef CONFIG_SYS_L2
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bl l2cache_disable_no_flush /* uses r3 */
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#endif
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mtlr r4 /* restore link register */
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blr
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/*
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* Is data cache enabled?
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*/
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_GLOBAL(dcache_status)
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mfspr r3, HID0
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andi. r3, r3, HID0_DCE
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blr
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/*
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* Invalidate L2 cache using L2I, assume L2 is enabled
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*/
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_GLOBAL(l2cache_invalidate)
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mfspr r3, l2cr
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rlwinm. r3, r3, 0, 0, 0
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beq 1f
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mfspr r3, l2cr
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rlwinm r3, r3, 0, 1, 31
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#ifdef CONFIG_ALTIVEC
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dssall
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#endif
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sync
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mtspr l2cr, r3
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sync
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1: mfspr r3, l2cr
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oris r3, r3, L2CR_L2I@h
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mtspr l2cr, r3
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invl2:
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mfspr r3, l2cr
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andis. r3, r3, L2CR_L2I@h
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bne invl2
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blr
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/*
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* Enable L2 cache
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* Calls l2cache_invalidate. LR is saved in r4
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*/
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_GLOBAL(l2cache_enable)
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mflr r4 /* save link register */
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bl l2cache_invalidate /* uses r3 */
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sync
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lis r3, L2_ENABLE@h
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ori r3, r3, L2_ENABLE@l
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mtspr l2cr, r3
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isync
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mtlr r4 /* restore link register */
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blr
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/*
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* Disable L2 cache
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* Calls flush_dcache. LR is saved in r4
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*/
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_GLOBAL(l2cache_disable)
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mflr r4 /* save link register */
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bl flush_dcache /* uses r3 and r5 */
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sync
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mtlr r4 /* restore link register */
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l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
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lis r3, L2_INIT@h
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ori r3, r3, L2_INIT@l
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mtspr l2cr, r3
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isync
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blr
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