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	Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
		
			
				
	
	
		
			262 lines
		
	
	
		
			6.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			262 lines
		
	
	
		
			6.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /**
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|  * @file IxEthAcc.c
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|  *
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|  * @author Intel Corporation
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|  * @date 20-Feb-2001
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|  *
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|  * @brief This file contains the implementation of the IXP425 Ethernet Access Component
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|  *
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|  * Design Notes:
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|  *
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|  * @par
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|  * IXP400 SW Release version 2.0
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|  *
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|  * -- Copyright Notice --
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|  *
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|  * @par
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|  * Copyright 2001-2005, Intel Corporation.
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|  * All rights reserved.
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|  *
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|  * @par
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|  * Redistribution and use in source and binary forms, with or without
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|  * modification, are permitted provided that the following conditions
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|  * are met:
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|  * 1. Redistributions of source code must retain the above copyright
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|  *    notice, this list of conditions and the following disclaimer.
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|  * 2. Redistributions in binary form must reproduce the above copyright
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|  *    notice, this list of conditions and the following disclaimer in the
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|  *    documentation and/or other materials provided with the distribution.
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|  * 3. Neither the name of the Intel Corporation nor the names of its contributors
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|  *    may be used to endorse or promote products derived from this software
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|  *    without specific prior written permission.
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|  *
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|  * @par
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|  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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|  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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|  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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|  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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|  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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|  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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|  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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|  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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|  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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|  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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|  * SUCH DAMAGE.
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|  *
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|  * @par
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|  * -- End of Copyright Notice --
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|  */
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| 
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| 
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| 
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| #include "IxEthAcc.h"
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| #ifdef CONFIG_IXP425_COMPONENT_ETHDB
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| #include "IxEthDB.h"
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| #endif
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| #include "IxFeatureCtrl.h"
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| 
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| #include "IxEthAcc_p.h"
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| #include "IxEthAccMac_p.h"
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| #include "IxEthAccMii_p.h"
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| 
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| /**
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|  * @addtogroup IxEthAcc
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|  *@{
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|  */
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| 
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| 
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| /**
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|  * @brief System-wide information data strucure.
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|  *
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|  * @ingroup IxEthAccPri
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|  *
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|  */
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| 
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| IxEthAccInfo ixEthAccDataInfo;
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| extern PUBLIC IxEthAccMacState ixEthAccMacState[];
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| extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
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| 
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| /**
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|  * @brief System-wide information
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|  *
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|  * @ingroup IxEthAccPri
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|  *
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|  */
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| BOOL ixEthAccServiceInit = FALSE;
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| 
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| /* global filtering bit mask */
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| PUBLIC UINT32 ixEthAccNewSrcMask;
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| 
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| /**
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|  * @brief Per port information data strucure.
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|  *
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|  * @ingroup IxEthAccPri
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|  *
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|  */
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| 
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| IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
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| 
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| PUBLIC IxEthAccStatus ixEthAccInit()
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| {
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| #ifdef CONFIG_IXP425_COMPONENT_ETHDB
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|   /*
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|    * Initialize Control plane
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|    */
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|   if (ixEthDBInit() != IX_ETH_DB_SUCCESS)
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|   {
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|       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
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| 
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|       return IX_ETH_ACC_FAIL;
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|   }
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| #endif
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| 
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|   if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
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|   {
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|       ixEthAccNewSrcMask = (~0); /* want all the bits */
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|   }
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|   else
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|   {
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|       ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
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|   }
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| 
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|   /*
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|    * Initialize Data plane
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|    */
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|    if ( ixEthAccInitDataPlane()  != IX_ETH_ACC_SUCCESS )
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|    {
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|       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
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| 
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|        return IX_ETH_ACC_FAIL;
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|    }
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| 
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| 
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|    if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
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|    {
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|       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
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| 
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|        return IX_ETH_ACC_FAIL;
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|    }
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| 
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|    /*
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|     * Initialize MII
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|     */
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|    if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
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|    {
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|       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
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| 
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|        return IX_ETH_ACC_FAIL;
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|    }
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| 
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|    /*
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|     * Initialize MAC I/O memory
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|     */
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|    if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
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|    {
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|       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
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| 
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|      return IX_ETH_ACC_FAIL;
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|    }
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| 
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|    /*
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|     * Initialize control plane interface lock
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|     */
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|    if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
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|    {
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|        IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
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| 
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|        return IX_ETH_ACC_FAIL;
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|    }
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| 
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|    /* initialiasation is complete */
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|    ixEthAccServiceInit = TRUE;
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| 
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|    return IX_ETH_ACC_SUCCESS;
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| 
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| }
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| 
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| PUBLIC void ixEthAccUnload(void)
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| {
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|     IxEthAccPortId portId;
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| 
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|     if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
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|     {
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|        /* check none of the port is still active */
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|        for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
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|        {
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| 	   if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
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| 	   {
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| 	       if (ixEthAccMacState[portId].portDisableState == ACTIVE)
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| 	       {
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| 		   IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
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| 		   return;
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| 	       }
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| 	   }
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|        }
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| 
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|        /* unmap the memory areas */
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|        ixEthAccMiiUnload();
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|        ixEthAccMacUnload();
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| 
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|        /* set all ports as uninitialized */
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|        for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
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|        {
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| 	       ixEthAccPortData[portId].portInitialized = FALSE;
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|        }
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| 
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|        /* uninitialize the service */
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|        ixEthAccServiceInit = FALSE;
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|    }
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| }
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| 
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| PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
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| {
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| 
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|   IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
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| 
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|    if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
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|    {
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| 	return(IX_ETH_ACC_FAIL);
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|    }
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| 
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|    /*
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|     * Check for valid port
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|     */
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| 
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|    if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
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|    {
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|        return (IX_ETH_ACC_INVALID_PORT);
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|    }
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| 
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|    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
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|    {
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|        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
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|        return IX_ETH_ACC_SUCCESS ;
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|    }
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| 
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|    if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
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|    {
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| 	/* Already initialized */
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| 	return(IX_ETH_ACC_FAIL);
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|    }
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| 
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|    if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
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|    {
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|        return IX_ETH_ACC_FAIL;
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|    }
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| 
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|    /*
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|      * Set the port init flag.
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|      */
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| 
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|     ixEthAccPortData[portId].portInitialized = TRUE;
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| 
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| #ifdef CONFIG_IXP425_COMPONENT_ETHDB
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|     /* init learning/filtering database structures for this port */
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|     ixEthDBPortInit(portId);
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| #endif
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| 
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|     return(ret);
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| }
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| 
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| 
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