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fe3334d0a3
Import misc remaining header files from 2013 U-Boot. These will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
79 lines
3.4 KiB
C
79 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Configuration and status register (CSR) address and type definitions for
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* Octoen.
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*/
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#ifndef __CVMX_CSR_H__
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#define __CVMX_CSR_H__
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#include "cvmx-csr-enums.h"
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#include "cvmx-pip-defs.h"
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typedef cvmx_pip_prt_cfgx_t cvmx_pip_port_cfg_t;
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/* The CSRs for bootbus region zero used to be independent of the
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other 1-7. As of SDK 1.7.0 these were combined. These macros
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are for backwards compactability */
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#define CVMX_MIO_BOOT_REG_CFG0 CVMX_MIO_BOOT_REG_CFGX(0)
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#define CVMX_MIO_BOOT_REG_TIM0 CVMX_MIO_BOOT_REG_TIMX(0)
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/* The CN3XXX and CN58XX chips used to not have a LMC number
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passed to the address macros. These are here to supply backwards
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compatibility with old code. Code should really use the new addresses
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with bus arguments for support on other chips */
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#define CVMX_LMC_BIST_CTL CVMX_LMCX_BIST_CTL(0)
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#define CVMX_LMC_BIST_RESULT CVMX_LMCX_BIST_RESULT(0)
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#define CVMX_LMC_COMP_CTL CVMX_LMCX_COMP_CTL(0)
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#define CVMX_LMC_CTL CVMX_LMCX_CTL(0)
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#define CVMX_LMC_CTL1 CVMX_LMCX_CTL1(0)
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#define CVMX_LMC_DCLK_CNT_HI CVMX_LMCX_DCLK_CNT_HI(0)
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#define CVMX_LMC_DCLK_CNT_LO CVMX_LMCX_DCLK_CNT_LO(0)
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#define CVMX_LMC_DCLK_CTL CVMX_LMCX_DCLK_CTL(0)
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#define CVMX_LMC_DDR2_CTL CVMX_LMCX_DDR2_CTL(0)
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#define CVMX_LMC_DELAY_CFG CVMX_LMCX_DELAY_CFG(0)
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#define CVMX_LMC_DLL_CTL CVMX_LMCX_DLL_CTL(0)
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#define CVMX_LMC_DUAL_MEMCFG CVMX_LMCX_DUAL_MEMCFG(0)
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#define CVMX_LMC_ECC_SYND CVMX_LMCX_ECC_SYND(0)
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#define CVMX_LMC_FADR CVMX_LMCX_FADR(0)
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#define CVMX_LMC_IFB_CNT_HI CVMX_LMCX_IFB_CNT_HI(0)
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#define CVMX_LMC_IFB_CNT_LO CVMX_LMCX_IFB_CNT_LO(0)
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#define CVMX_LMC_MEM_CFG0 CVMX_LMCX_MEM_CFG0(0)
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#define CVMX_LMC_MEM_CFG1 CVMX_LMCX_MEM_CFG1(0)
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#define CVMX_LMC_OPS_CNT_HI CVMX_LMCX_OPS_CNT_HI(0)
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#define CVMX_LMC_OPS_CNT_LO CVMX_LMCX_OPS_CNT_LO(0)
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#define CVMX_LMC_PLL_BWCTL CVMX_LMCX_PLL_BWCTL(0)
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#define CVMX_LMC_PLL_CTL CVMX_LMCX_PLL_CTL(0)
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#define CVMX_LMC_PLL_STATUS CVMX_LMCX_PLL_STATUS(0)
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#define CVMX_LMC_READ_LEVEL_CTL CVMX_LMCX_READ_LEVEL_CTL(0)
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#define CVMX_LMC_READ_LEVEL_DBG CVMX_LMCX_READ_LEVEL_DBG(0)
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#define CVMX_LMC_READ_LEVEL_RANKX CVMX_LMCX_READ_LEVEL_RANKX(0)
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#define CVMX_LMC_RODT_COMP_CTL CVMX_LMCX_RODT_COMP_CTL(0)
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#define CVMX_LMC_RODT_CTL CVMX_LMCX_RODT_CTL(0)
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#define CVMX_LMC_WODT_CTL CVMX_LMCX_WODT_CTL0(0)
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#define CVMX_LMC_WODT_CTL0 CVMX_LMCX_WODT_CTL0(0)
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#define CVMX_LMC_WODT_CTL1 CVMX_LMCX_WODT_CTL1(0)
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/* The CN3XXX and CN58XX chips used to not have a TWSI bus number
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passed to the address macros. These are here to supply backwards
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compatibility with old code. Code should really use the new addresses
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with bus arguments for support on other chips */
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#define CVMX_MIO_TWS_INT CVMX_MIO_TWSX_INT(0)
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#define CVMX_MIO_TWS_SW_TWSI CVMX_MIO_TWSX_SW_TWSI(0)
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#define CVMX_MIO_TWS_SW_TWSI_EXT CVMX_MIO_TWSX_SW_TWSI_EXT(0)
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#define CVMX_MIO_TWS_TWSI_SW CVMX_MIO_TWSX_TWSI_SW(0)
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/* The CN3XXX and CN58XX chips used to not have a SMI/MDIO bus number
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passed to the address macros. These are here to supply backwards
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compatibility with old code. Code should really use the new addresses
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with bus arguments for support on other chips */
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#define CVMX_SMI_CLK CVMX_SMIX_CLK(0)
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#define CVMX_SMI_CMD CVMX_SMIX_CMD(0)
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#define CVMX_SMI_EN CVMX_SMIX_EN(0)
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#define CVMX_SMI_RD_DAT CVMX_SMIX_RD_DAT(0)
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#define CVMX_SMI_WR_DAT CVMX_SMIX_WR_DAT(0)
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#endif /* __CVMX_CSR_H__ */
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