mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 12:08:19 +00:00
5a8dbdc6b4
Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
25 lines
926 B
Plaintext
25 lines
926 B
Plaintext
Freescale esdhc-specific options
|
|
|
|
- CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
Support Freescale adapter card type identification. This is implemented by
|
|
operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
|
|
Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot.
|
|
|
|
SDHC Card ID[0:2] Adapter Card Type
|
|
0b000 reserved
|
|
0b001 eMMC Card Rev4.5
|
|
0b010 SD/MMC Legacy Card
|
|
0b011 eMMC Card Rev4.4
|
|
0b100 reserved
|
|
0b101 MMC Card
|
|
0b110 SD Card Rev2.0/3.0
|
|
0b111 No card is present
|
|
- CONFIG_SYS_FSL_ESDHC_LE
|
|
ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
|
|
determined by ESDHC IP's endian mode or processor's endian mode.
|
|
- CONFIG_SYS_FSL_ESDHC_BE
|
|
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
|
|
by ESDHC IP's endian mode or processor's endian mode.
|
|
|
|
- CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
|