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Marek Vasut df155672ff spi: altera: Add short note about EPCS/EPCQx1

Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

2014-10-27 22:37:03 +05:30

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 SoCFPGA EPCS/EPCQx1 mini howto:
 - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
 - The controller base address is the "Base" in QSys + 0x400
 - Set MSEL[4:0]=10010 (AS Standard)
 - Load the bitstream into FPGA, enable bridges
 - Only then will the driver work