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f29eaadeb5
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*/
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/ {
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/* This should go only into devel boards */
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compatible = "marvell,cp110";
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sar {
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#address-cells = <1>;
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#size-cells = <0>;
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sar_fields {
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compatible = "marvell,sample-at-reset";
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reg = <0x4c 0x4e>;
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chip_count = <2>;
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bit_width = <5>;
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freq {
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key = "freq";
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description = "CPU/DDR and PIDI frequencies";
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start-bit = <0>;
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bit-length = <4>;
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option-cnt = <3>;
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options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz",
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"0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz",
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"0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz";
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default = <0x2>;
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status = "okay";
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};
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boot_mode {
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key = "boot_mode";
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description = "Boot mode options";
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start-bit = <4>;
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bit-length = <6>;
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option-cnt = <4>;
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options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)",
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"0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)",
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"0x2A", "AP_EMMC",
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"0x32", "CP1_SPI_1 24bits";
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default = <0x32>;
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status = "okay";
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};
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};
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};
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};
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