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	As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			151 lines
		
	
	
		
			3.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			151 lines
		
	
	
		
			3.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
// SPDX-License-Identifier: GPL-2.0+
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/*
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 *  (C) Copyright 2012-2013
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 *  NVIDIA Corporation <www.nvidia.com>
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 *
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 *  (C) Copyright 2022
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 *  Svyatoslav Ryhel <clamor95@gmail.com>
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 */
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/fuse.h>
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#include "cpu.h"
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#define FUSE_UID_LOW		0x108
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#define FUSE_UID_HIGH		0x10c
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#define FUSE_VENDOR_CODE	0x200
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#define FUSE_FAB_CODE		0x204
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#define FUSE_LOT_CODE_0		0x208
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#define FUSE_LOT_CODE_1		0x20c
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#define FUSE_WAFER_ID		0x210
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#define FUSE_X_COORDINATE	0x214
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#define FUSE_Y_COORDINATE	0x218
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#define FUSE_VENDOR_CODE_MASK	0xf
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#define FUSE_FAB_CODE_MASK	0x3f
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#define FUSE_WAFER_ID_MASK	0x3f
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#define FUSE_X_COORDINATE_MASK	0x1ff
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#define FUSE_Y_COORDINATE_MASK	0x1ff
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static u32 tegra_fuse_readl(unsigned long offset)
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{
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	return readl(NV_PA_FUSE_BASE + offset);
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}
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static void tegra_fuse_init(void)
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{
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	u32 reg;
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	/*
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	 * Performed by downstream and is not
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	 * documented by TRM. Whithout setting
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	 * this bit fuse region will not work.
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	 */
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	reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48);
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	reg |= BIT(28);
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	writel(reg, NV_PA_CLK_RST_BASE + 0x48);
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	clock_enable(PERIPH_ID_FUSE);
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	udelay(2);
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	reset_set_enable(PERIPH_ID_FUSE, 0);
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}
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unsigned long long tegra_chip_uid(void)
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{
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	u64 uid = 0ull;
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	u32 reg;
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	u32 cid;
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	u32 vendor;
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	u32 fab;
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	u32 lot;
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	u32 wafer;
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	u32 x;
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	u32 y;
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	u32 i;
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	tegra_fuse_init();
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	/* This used to be so much easier in prior chips. Unfortunately, there
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	   is no one-stop shopping for the unique id anymore. It must be
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	   constructed from various bits of information burned into the fuses
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	   during the manufacturing process. The 64-bit unique id is formed
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	   by concatenating several bit fields. The notation used for the
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	   various fields is <fieldname:size_in_bits> with the UID composed
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	   thusly:
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	   <CID:4><VENDOR:4><FAB:6><LOT:26><WAFER:6><X:9><Y:9>
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	   Where:
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		Field    Bits  Position Data
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		-------  ----  -------- ----------------------------------------
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		CID        4     60     Chip id
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		VENDOR     4     56     Vendor code
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		FAB        6     50     FAB code
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		LOT       26     24     Lot code (5-digit base-36-coded-decimal,
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					re-encoded to 26 bits binary)
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		WAFER      6     18     Wafer id
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		X          9      9     Wafer X-coordinate
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		Y          9      0     Wafer Y-coordinate
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		-------  ----
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		Total     64
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	*/
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	switch (tegra_get_chip()) {
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	case CHIPID_TEGRA20:
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		/* T20 has simple calculation */
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		return ((unsigned long long)tegra_fuse_readl(FUSE_UID_HIGH) << 32ull) |
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			(unsigned long long)tegra_fuse_readl(FUSE_UID_LOW);
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	case CHIPID_TEGRA30:
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		/* T30 chip id is 0 */
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		cid = 0;
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		break;
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	case CHIPID_TEGRA114:
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		/* T11x chip id is 1 */
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		cid = 1;
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		break;
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	case CHIPID_TEGRA124:
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		/* T12x chip id is 3 */
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		cid = 3;
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		break;
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	case CHIPID_TEGRA210:
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		/* T210 chip id is 5 */
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		cid = 5;
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	default:
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		return 0;
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	}
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	vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK;
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	fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK;
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	/* Lot code must be re-encoded from a 5 digit base-36 'BCD' number
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	   to a binary number. */
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	lot = 0;
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	reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2;
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	for (i = 0; i < 5; ++i) {
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		u32 digit = (reg & 0xFC000000) >> 26;
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		lot *= 36;
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		lot += digit;
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		reg <<= 6;
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	}
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	wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK;
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	x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK;
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	y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK;
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	uid = ((unsigned long long)cid  << 60ull)
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	    | ((unsigned long long)vendor << 56ull)
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	    | ((unsigned long long)fab << 50ull)
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	    | ((unsigned long long)lot << 24ull)
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	    | ((unsigned long long)wafer << 18ull)
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	    | ((unsigned long long)x << 9ull)
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	    | ((unsigned long long)y << 0ull);
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	return uid;
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}
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