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684af0be94
Sync with kernel dts by adding pinmuxes for mmc1 and mmc2. This fixes an issue where mmc2 (eMMC) was coming up in HS52 mode instead of the highest DDR52 mode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
38 lines
723 B
Plaintext
38 lines
723 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "dra76x.dtsi"
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#include "dra7-mmc-iodelay.dtsi"
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#include "dra76x-mmc-iodelay.dtsi"
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#include "am572x-idk-common.dtsi"
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/ {
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model = "TI AM5748 IDK";
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compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
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};
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&qspi {
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spi-max-frequency = <96000000>;
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m25p80@0 {
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spi-max-frequency = <96000000>;
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};
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};
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&mmc1 {
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pinctrl-names = "default", "hs";
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pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
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pinctrl-1 = <&mmc1_pins_hs>;
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};
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&mmc2 {
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pinctrl-names = "default", "hs", "ddr_1_8v";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_default>;
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pinctrl-2 = <&mmc2_pins_default>;
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};
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