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e04f9d0c2f
This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
63 lines
1.8 KiB
C
63 lines
1.8 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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extern void erratum_a008850_post(void);
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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u32 cpo_override;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
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*/
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#ifdef CONFIG_SYS_FSL_DDR4
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{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
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{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
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{1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
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{1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
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#elif defined(CONFIG_SYS_FSL_DDR3)
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{1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
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{1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
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{1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
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{2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
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{2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
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{2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
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#else
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#error DDR type not defined
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#endif
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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