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	On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
		
			
				
	
	
		
			198 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			198 lines
		
	
	
		
			5.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2015-2016 Socionext Inc.
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|  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <linux/io.h>
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| #include <linux/err.h>
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| #include <linux/sizes.h>
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| #include <dm/device.h>
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| #include <dm/pinctrl.h>
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| 
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| #include "pinctrl-uniphier.h"
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| 
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| #define UNIPHIER_PINCTRL_PINMUX_BASE	0x1000
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| #define UNIPHIER_PINCTRL_LOAD_PINMUX	0x1700
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| #define UNIPHIER_PINCTRL_IECTRL		0x1d00
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| 
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| static const char *uniphier_pinctrl_dummy_name = "_dummy";
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| 
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| static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 
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| 	return priv->socdata->groups_count;
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| }
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| 
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| static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
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| 						   unsigned selector)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 
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| 	if (!priv->socdata->groups[selector].name)
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| 		return uniphier_pinctrl_dummy_name;
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| 
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| 	return priv->socdata->groups[selector].name;
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| }
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| 
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| static int uniphier_pinmux_get_functions_count(struct udevice *dev)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 
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| 	return priv->socdata->functions_count;
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| }
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| 
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| static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
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| 						     unsigned selector)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 
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| 	if (!priv->socdata->functions[selector])
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| 		return uniphier_pinctrl_dummy_name;
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| 
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| 	return priv->socdata->functions[selector];
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| }
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| 
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| static void uniphier_pinconf_input_enable_perpin(struct udevice *dev,
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| 						 unsigned pin)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 	unsigned reg;
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| 	u32 mask, tmp;
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| 
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| 	reg = UNIPHIER_PINCTRL_IECTRL + pin / 32 * 4;
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| 	mask = BIT(pin % 32);
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| 
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| 	tmp = readl(priv->base + reg);
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| 	tmp |= mask;
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| 	writel(tmp, priv->base + reg);
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| }
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| 
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| static void uniphier_pinconf_input_enable_legacy(struct udevice *dev,
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| 						 unsigned pin)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 	int pins_count = priv->socdata->pins_count;
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| 	const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
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| 	int i;
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| 
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| 	for (i = 0; i < pins_count; i++) {
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| 		if (pins[i].number == pin) {
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| 			unsigned int iectrl;
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| 			u32 tmp;
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| 
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| 			iectrl = uniphier_pin_get_iectrl(pins[i].data);
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| 			tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL);
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| 			tmp |= 1 << iectrl;
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| 			writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL);
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| 		}
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| 	}
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| }
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| 
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| static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 
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| 	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
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| 		uniphier_pinconf_input_enable_perpin(dev, pin);
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| 	else
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| 		uniphier_pinconf_input_enable_legacy(dev, pin);
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| }
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| 
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| static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
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| 				    int muxval)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 	unsigned reg, reg_end, shift, mask;
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| 	unsigned mux_bits = 8;
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| 	unsigned reg_stride = 4;
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| 	bool load_pinctrl = false;
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| 	u32 tmp;
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| 
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| 	/* some pins need input-enabling */
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| 	uniphier_pinconf_input_enable(dev, pin);
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| 
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| 	if (muxval < 0)
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| 		return;		/* dedicated pin; nothing to do for pin-mux */
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| 
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| 	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
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| 		mux_bits = 4;
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| 
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| 	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
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| 		/*
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| 		 *  Mode       offset        bit
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| 		 *  Normal     4 * n     shift+3:shift
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| 		 *  Debug      4 * n     shift+7:shift+4
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| 		 */
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| 		mux_bits /= 2;
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| 		reg_stride = 8;
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| 		load_pinctrl = true;
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| 	}
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| 
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| 	reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
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| 	reg_end = reg + reg_stride;
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| 	shift = pin * mux_bits % 32;
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| 	mask = (1U << mux_bits) - 1;
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| 
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| 	/*
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| 	 * If reg_stride is greater than 4, the MSB of each pinsel shall be
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| 	 * stored in the offset+4.
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| 	 */
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| 	for (; reg < reg_end; reg += 4) {
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| 		tmp = readl(priv->base + reg);
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| 		tmp &= ~(mask << shift);
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| 		tmp |= (mask & muxval) << shift;
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| 		writel(tmp, priv->base + reg);
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| 
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| 		muxval >>= mux_bits;
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| 	}
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| 
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| 	if (load_pinctrl)
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| 		writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
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| }
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| 
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| static int uniphier_pinmux_group_set(struct udevice *dev,
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| 				     unsigned group_selector,
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| 				     unsigned func_selector)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 	const struct uniphier_pinctrl_group *grp =
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| 					&priv->socdata->groups[group_selector];
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| 	int i;
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| 
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| 	for (i = 0; i < grp->num_pins; i++)
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| 		uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]);
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| 
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| 	return 0;
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| }
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| 
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| const struct pinctrl_ops uniphier_pinctrl_ops = {
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| 	.get_groups_count = uniphier_pinctrl_get_groups_count,
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| 	.get_group_name = uniphier_pinctrl_get_group_name,
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| 	.get_functions_count = uniphier_pinmux_get_functions_count,
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| 	.get_function_name = uniphier_pinmux_get_function_name,
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| 	.pinmux_group_set = uniphier_pinmux_group_set,
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| 	.set_state = pinctrl_generic_set_state,
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| };
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| 
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| int uniphier_pinctrl_probe(struct udevice *dev,
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| 			   struct uniphier_pinctrl_socdata *socdata)
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| {
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| 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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| 	fdt_addr_t addr;
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| 
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| 	addr = dev_get_addr(dev->parent);
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| 	if (addr == FDT_ADDR_T_NONE)
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| 		return -EINVAL;
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| 
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| 	priv->base = devm_ioremap(dev, addr, SZ_4K);
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| 	if (!priv->base)
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| 		return -ENOMEM;
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| 
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| 	priv->socdata = socdata;
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| 
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| 	return 0;
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| }
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