Ye Li 237ce9b6c4 imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD ...

iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

2023-03-29 20:15:42 +02:00

..

upower

imx8ulp: add upower api support

2021-08-09 14:46:51 +02:00

ahab.c

misc: imx: S400_API: Move S400 MU and API to a common place

2022-07-26 11:29:00 +02:00

cgc.c

imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init

2022-04-12 17:33:56 +02:00

clock.c

imx8ulp: clock: Fix lcd clock algo

2022-04-21 12:44:23 +02:00

iomux.c

arm: imx8ulp: add iomuxc support

2021-08-09 14:46:51 +02:00

Kconfig

imx: imx8ulp: add ND/LD clock

2022-04-12 17:33:56 +02:00

lowlevel_init.S

arm: imx8ulp: release and configure XRDC at early phase

2021-08-09 14:46:51 +02:00

Makefile

imx8ulp: add upower api support

2021-08-09 14:46:51 +02:00

pcc.c

imx: imx8ulp: add CAAM clock entry

2022-04-12 17:33:56 +02:00

rdc.c

imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD

2023-03-29 20:15:42 +02:00

soc.c

imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part

2023-03-29 20:15:42 +02:00