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	* Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems
		
			
				
	
	
		
			64 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			64 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * MCF5282 Internal Memory Map
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|  *
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|  * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| #ifndef __IMMAP_5282__
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| #define __IMMAP_5282__
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| 
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| 
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| /* Fast ethernet controller registers
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|  */
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| typedef struct fec {
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| 	uint	fec_ecntrl;		/* ethernet control register		*/
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| 	uint	fec_ievent;		/* interrupt event register		*/
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| 	uint	fec_imask;		/* interrupt mask register		*/
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| 	uint	fec_ivec;		/* interrupt level and vector status	*/
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| 	uint	fec_r_des_active;	/* Rx ring updated flag			*/
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| 	uint	fec_x_des_active;	/* Tx ring updated flag			*/
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| 	uint	res3[10];		/* reserved				*/
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| 	uint	fec_mii_data;		/* MII data register			*/
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| 	uint	fec_mii_speed;		/* MII speed control register		*/
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| 	uint	res4[17];		/* reserved				*/
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| 	uint	fec_r_bound;		/* end of RAM (read-only)		*/
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| 	uint	fec_r_fstart;		/* Rx FIFO start address		*/
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| 	uint	res5[6];		/* reserved				*/
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| 	uint	fec_x_fstart;		/* Tx FIFO start address		*/
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| 	uint	res7[21];		/* reserved				*/
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| 	uint	fec_r_cntrl;		/* Rx control register			*/
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| 	uint	fec_r_hash;		/* Rx hash register			*/
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| 	uint	res8[14];		/* reserved				*/
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| 	uint	fec_x_cntrl;		/* Tx control register			*/
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| 	uint	res9[0x9e];		/* reserved				*/
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| 	uint	fec_addr_low;		/* lower 32 bits of station address	*/
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| 	uint	fec_addr_high;		/* upper 16 bits of station address	*/
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| 	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
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| 	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
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| 	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
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| 	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
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| 	uint	fec_r_buff_size;	/* Rx buffer size			*/
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| 	uint	res2[9];		/* reserved				*/
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| 	uchar	fec_fifo[960];		/* fifo RAM				*/
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| } fec_t;
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| 
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| #endif /* __IMMAP_5282__ */
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