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9819fe345c
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
212 lines
3.4 KiB
Plaintext
212 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2018
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*/
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#include <linux/stringify.h>
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&ddr {
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config-DDR_MEM_COMPATIBLE {
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u-boot,dm-pre-reloc;
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compatible = __stringify(st,DDR_MEM_COMPATIBLE);
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st,mem-name = DDR_MEM_NAME;
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st,mem-speed = <DDR_MEM_SPEED>;
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st,mem-size = <DDR_MEM_SIZE>;
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st,ctl-reg = <
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DDR_MSTR
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DDR_MRCTRL0
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DDR_MRCTRL1
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DDR_DERATEEN
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DDR_DERATEINT
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DDR_PWRCTL
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DDR_PWRTMG
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DDR_HWLPCTL
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DDR_RFSHCTL0
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DDR_RFSHCTL3
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DDR_CRCPARCTL0
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DDR_ZQCTL0
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DDR_DFITMG0
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DDR_DFITMG1
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DDR_DFILPCFG0
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DDR_DFIUPD0
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DDR_DFIUPD1
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DDR_DFIUPD2
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DDR_DFIPHYMSTR
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DDR_ODTMAP
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DDR_DBG0
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DDR_DBG1
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DDR_DBGCMD
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DDR_POISONCFG
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DDR_PCCFG
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>;
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st,ctl-timing = <
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DDR_RFSHTMG
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DDR_DRAMTMG0
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DDR_DRAMTMG1
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DDR_DRAMTMG2
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DDR_DRAMTMG3
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DDR_DRAMTMG4
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DDR_DRAMTMG5
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DDR_DRAMTMG6
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DDR_DRAMTMG7
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DDR_DRAMTMG8
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DDR_DRAMTMG14
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DDR_ODTCFG
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>;
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st,ctl-map = <
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DDR_ADDRMAP1
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DDR_ADDRMAP2
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DDR_ADDRMAP3
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DDR_ADDRMAP4
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DDR_ADDRMAP5
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DDR_ADDRMAP6
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DDR_ADDRMAP9
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DDR_ADDRMAP10
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DDR_ADDRMAP11
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>;
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st,ctl-perf = <
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DDR_SCHED
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DDR_SCHED1
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DDR_PERFHPR1
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DDR_PERFLPR1
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DDR_PERFWR1
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DDR_PCFGR_0
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DDR_PCFGW_0
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DDR_PCFGQOS0_0
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DDR_PCFGQOS1_0
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DDR_PCFGWQOS0_0
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DDR_PCFGWQOS1_0
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DDR_PCFGR_1
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DDR_PCFGW_1
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DDR_PCFGQOS0_1
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DDR_PCFGQOS1_1
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DDR_PCFGWQOS0_1
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DDR_PCFGWQOS1_1
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>;
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st,phy-reg = <
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DDR_PGCR
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DDR_ACIOCR
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DDR_DXCCR
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DDR_DSGCR
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DDR_DCR
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DDR_ODTCR
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DDR_ZQ0CR1
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DDR_DX0GCR
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DDR_DX1GCR
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DDR_DX2GCR
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DDR_DX3GCR
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>;
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st,phy-timing = <
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DDR_PTR0
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DDR_PTR1
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DDR_PTR2
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DDR_DTPR0
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DDR_DTPR1
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DDR_DTPR2
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DDR_MR0
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DDR_MR1
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DDR_MR2
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DDR_MR3
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>;
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status = "okay";
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};
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};
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#undef DDR_MEM_COMPATIBLE
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#undef DDR_MEM_NAME
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#undef DDR_MEM_SPEED
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#undef DDR_MEM_SIZE
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#undef DDR_MSTR
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#undef DDR_MRCTRL0
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#undef DDR_MRCTRL1
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#undef DDR_DERATEEN
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#undef DDR_DERATEINT
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#undef DDR_PWRCTL
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#undef DDR_PWRTMG
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#undef DDR_HWLPCTL
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#undef DDR_RFSHCTL0
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#undef DDR_RFSHCTL3
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#undef DDR_RFSHTMG
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#undef DDR_CRCPARCTL0
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#undef DDR_DRAMTMG0
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#undef DDR_DRAMTMG1
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#undef DDR_DRAMTMG2
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#undef DDR_DRAMTMG3
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#undef DDR_DRAMTMG4
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#undef DDR_DRAMTMG5
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#undef DDR_DRAMTMG6
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#undef DDR_DRAMTMG7
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#undef DDR_DRAMTMG8
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#undef DDR_DRAMTMG14
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#undef DDR_ZQCTL0
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#undef DDR_DFITMG0
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#undef DDR_DFITMG1
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#undef DDR_DFILPCFG0
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#undef DDR_DFIUPD0
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#undef DDR_DFIUPD1
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#undef DDR_DFIUPD2
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#undef DDR_DFIPHYMSTR
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#undef DDR_ADDRMAP1
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#undef DDR_ADDRMAP2
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#undef DDR_ADDRMAP3
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#undef DDR_ADDRMAP4
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#undef DDR_ADDRMAP5
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#undef DDR_ADDRMAP6
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#undef DDR_ADDRMAP9
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#undef DDR_ADDRMAP10
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#undef DDR_ADDRMAP11
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#undef DDR_ODTCFG
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#undef DDR_ODTMAP
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#undef DDR_SCHED
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#undef DDR_SCHED1
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#undef DDR_PERFHPR1
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#undef DDR_PERFLPR1
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#undef DDR_PERFWR1
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#undef DDR_DBG0
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#undef DDR_DBG1
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#undef DDR_DBGCMD
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#undef DDR_POISONCFG
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#undef DDR_PCCFG
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#undef DDR_PCFGR_0
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#undef DDR_PCFGW_0
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#undef DDR_PCFGQOS0_0
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#undef DDR_PCFGQOS1_0
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#undef DDR_PCFGWQOS0_0
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#undef DDR_PCFGWQOS1_0
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#undef DDR_PCFGR_1
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#undef DDR_PCFGW_1
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#undef DDR_PCFGQOS0_1
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#undef DDR_PCFGQOS1_1
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#undef DDR_PCFGWQOS0_1
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#undef DDR_PCFGWQOS1_1
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#undef DDR_PGCR
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#undef DDR_PTR0
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#undef DDR_PTR1
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#undef DDR_PTR2
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#undef DDR_ACIOCR
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#undef DDR_DXCCR
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#undef DDR_DSGCR
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#undef DDR_DCR
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#undef DDR_DTPR0
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#undef DDR_DTPR1
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#undef DDR_DTPR2
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#undef DDR_MR0
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#undef DDR_MR1
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#undef DDR_MR2
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#undef DDR_MR3
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#undef DDR_ODTCR
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#undef DDR_ZQ0CR1
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#undef DDR_DX0GCR
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#undef DDR_DX1GCR
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#undef DDR_DX2GCR
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#undef DDR_DX3GCR
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