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1626308797
Recieve/Receive recieve/receive Interupt/Interrupt interupt/interrupt Addres/Address addres/address Signed-off-by: Mike Williams <mike@mikebwilliams.com>
517 lines
16 KiB
C
517 lines
16 KiB
C
/**
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* @file IxQueueAssignments.h
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*
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* @author Intel Corporation
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* @date 29-Oct-2004
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*
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* @brief Central definition for queue assignments
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*
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* Design Notes:
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* This file contains queue assignments used by Ethernet (EthAcc),
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* HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
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*
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* Note: Ethernet QoS traffic class definitions are managed separately
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* by EthDB in IxEthDBQoS.h.
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IxQueueAssignments_H
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#define IxQueueAssignments_H
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#include "IxQMgr.h"
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/***************************************************************************
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* Queue assignments for ATM
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***************************************************************************/
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/**
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* @brief Global compiler switch to select between 3 possible NPE Modes
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* Define this macro to enable MPHY mode
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*
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* Default(No Switch) = MultiPHY Utopia2
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* IX_UTOPIAMODE = 1 for single Phy Utopia1
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* IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
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*/
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#define IX_NPE_MPHYMULTIPORT 1
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#if IX_UTOPIAMODE == 1
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#undef IX_NPE_MPHYMULTIPORT
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#endif
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#if IX_MPHYSINGLEPORT == 1
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#undef IX_NPE_MPHYMULTIPORT
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#endif
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/**
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* @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
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*
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* @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
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*/
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#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK 2
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/**
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* @def IX_NPE_A_QMQ_ATM_TX_DONE
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*
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* @brief Queue ID for ATM Transmit Done queue
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*/
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#define IX_NPE_A_QMQ_ATM_TX_DONE IX_QMGR_QUEUE_1
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/**
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* @def IX_NPE_A_QMQ_ATM_TX0
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*
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* @brief Queue ID for ATM transmit Queue in a single phy configuration
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*/
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#define IX_NPE_A_QMQ_ATM_TX0 IX_QMGR_QUEUE_2
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/**
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* @def IX_NPE_A_QMQ_ATM_TXID_MIN
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*
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* @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
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*
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*/
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/**
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* @def IX_NPE_A_QMQ_ATM_TXID_MAX
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*
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* @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
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*
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*/
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/**
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* @def IX_NPE_A_QMQ_ATM_RX_HI
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*
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* @brief Queue Manager Queue ID for ATM Receive high Queue
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*
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*/
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/**
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* @def IX_NPE_A_QMQ_ATM_RX_LO
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*
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* @brief Queue Manager Queue ID for ATM Receive low Queue
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*/
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#ifdef IX_NPE_MPHYMULTIPORT
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/**
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* @def IX_NPE_A_QMQ_ATM_TX1
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*
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* @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
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*/
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#define IX_NPE_A_QMQ_ATM_TX1 IX_NPE_A_QMQ_ATM_TX0+1
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#define IX_NPE_A_QMQ_ATM_TX2 IX_NPE_A_QMQ_ATM_TX1+1
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#define IX_NPE_A_QMQ_ATM_TX3 IX_NPE_A_QMQ_ATM_TX2+1
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#define IX_NPE_A_QMQ_ATM_TX4 IX_NPE_A_QMQ_ATM_TX3+1
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#define IX_NPE_A_QMQ_ATM_TX5 IX_NPE_A_QMQ_ATM_TX4+1
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#define IX_NPE_A_QMQ_ATM_TX6 IX_NPE_A_QMQ_ATM_TX5+1
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#define IX_NPE_A_QMQ_ATM_TX7 IX_NPE_A_QMQ_ATM_TX6+1
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#define IX_NPE_A_QMQ_ATM_TX8 IX_NPE_A_QMQ_ATM_TX7+1
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#define IX_NPE_A_QMQ_ATM_TX9 IX_NPE_A_QMQ_ATM_TX8+1
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#define IX_NPE_A_QMQ_ATM_TX10 IX_NPE_A_QMQ_ATM_TX9+1
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#define IX_NPE_A_QMQ_ATM_TX11 IX_NPE_A_QMQ_ATM_TX10+1
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#define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
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#define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX11
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#define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_21
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#define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_22
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#else
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#define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
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#define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX0
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#define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_10
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#define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_11
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#endif /* MPHY */
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/**
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* @def IX_NPE_A_QMQ_ATM_FREE_VC0
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*
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* @brief Hardware QMgr Queue ID for ATM Free VC Queue.
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*
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* There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
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* IX_NPE_A_QMQ_ATM_FREE_VC30
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*/
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#define IX_NPE_A_QMQ_ATM_FREE_VC0 IX_QMGR_QUEUE_32
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#define IX_NPE_A_QMQ_ATM_FREE_VC1 IX_NPE_A_QMQ_ATM_FREE_VC0+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC2 IX_NPE_A_QMQ_ATM_FREE_VC1+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC3 IX_NPE_A_QMQ_ATM_FREE_VC2+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC4 IX_NPE_A_QMQ_ATM_FREE_VC3+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC5 IX_NPE_A_QMQ_ATM_FREE_VC4+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC6 IX_NPE_A_QMQ_ATM_FREE_VC5+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC7 IX_NPE_A_QMQ_ATM_FREE_VC6+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC8 IX_NPE_A_QMQ_ATM_FREE_VC7+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC9 IX_NPE_A_QMQ_ATM_FREE_VC8+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC10 IX_NPE_A_QMQ_ATM_FREE_VC9+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC11 IX_NPE_A_QMQ_ATM_FREE_VC10+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC12 IX_NPE_A_QMQ_ATM_FREE_VC11+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC13 IX_NPE_A_QMQ_ATM_FREE_VC12+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC14 IX_NPE_A_QMQ_ATM_FREE_VC13+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC15 IX_NPE_A_QMQ_ATM_FREE_VC14+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC16 IX_NPE_A_QMQ_ATM_FREE_VC15+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC17 IX_NPE_A_QMQ_ATM_FREE_VC16+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC18 IX_NPE_A_QMQ_ATM_FREE_VC17+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC19 IX_NPE_A_QMQ_ATM_FREE_VC18+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC20 IX_NPE_A_QMQ_ATM_FREE_VC19+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC21 IX_NPE_A_QMQ_ATM_FREE_VC20+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC22 IX_NPE_A_QMQ_ATM_FREE_VC21+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC23 IX_NPE_A_QMQ_ATM_FREE_VC22+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC24 IX_NPE_A_QMQ_ATM_FREE_VC23+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC25 IX_NPE_A_QMQ_ATM_FREE_VC24+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC26 IX_NPE_A_QMQ_ATM_FREE_VC25+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC27 IX_NPE_A_QMQ_ATM_FREE_VC26+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC28 IX_NPE_A_QMQ_ATM_FREE_VC27+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC29 IX_NPE_A_QMQ_ATM_FREE_VC28+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC30 IX_NPE_A_QMQ_ATM_FREE_VC29+1
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#define IX_NPE_A_QMQ_ATM_FREE_VC31 IX_NPE_A_QMQ_ATM_FREE_VC30+1
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/**
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* @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
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*
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* @brief The minimum queue ID for FreeVC queue
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*/
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#define IX_NPE_A_QMQ_ATM_RXFREE_MIN IX_NPE_A_QMQ_ATM_FREE_VC0
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/**
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* @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
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*
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* @brief The maximum queue ID for FreeVC queue
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*/
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#define IX_NPE_A_QMQ_ATM_RXFREE_MAX IX_NPE_A_QMQ_ATM_FREE_VC31
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/**
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* @def IX_NPE_A_QMQ_OAM_FREE_VC
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* @brief OAM Rx Free queue ID
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*/
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#ifdef IX_NPE_MPHYMULTIPORT
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#define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_14
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#else
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#define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_3
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#endif /* MPHY */
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/****************************************************************************
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* Queue assignments for HSS
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****************************************************************************/
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/**** HSS Port 0 ****/
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/**
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* @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
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*/
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#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG IX_QMGR_QUEUE_12
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_RX
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_RX IX_QMGR_QUEUE_13
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_TX0
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_TX0 IX_QMGR_QUEUE_14
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_TX1
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_TX1 IX_QMGR_QUEUE_15
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_TX2
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_TX2 IX_QMGR_QUEUE_16
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_TX3
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_TX3 IX_QMGR_QUEUE_17
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0 IX_QMGR_QUEUE_18
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1 IX_QMGR_QUEUE_19
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2 IX_QMGR_QUEUE_20
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3 IX_QMGR_QUEUE_21
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/**
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* @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
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*
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* @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
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*/
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#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE IX_QMGR_QUEUE_22
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/**** HSS Port 1 ****/
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/**
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* @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
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*/
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#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG IX_QMGR_QUEUE_10
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_RX
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_RX IX_QMGR_QUEUE_0
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_TX0
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_TX0 IX_QMGR_QUEUE_5
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_TX1
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_TX1 IX_QMGR_QUEUE_6
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_TX2
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_TX2 IX_QMGR_QUEUE_7
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_TX3
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_TX3 IX_QMGR_QUEUE_8
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0 IX_QMGR_QUEUE_1
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1 IX_QMGR_QUEUE_2
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2 IX_QMGR_QUEUE_3
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3 IX_QMGR_QUEUE_4
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/**
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* @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
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*
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* @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
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*/
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#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE IX_QMGR_QUEUE_9
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/*****************************************************************************************
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* Queue assignments for DMA
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*****************************************************************************************/
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#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19 /**< Queue Id for NPE A DMA Request */
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#define IX_DMA_NPE_A_DONE_QID IX_QMGR_QUEUE_20 /**< Queue Id for NPE A DMA Done */
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#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24 /**< Queue Id for NPE B DMA Request */
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#define IX_DMA_NPE_B_DONE_QID IX_QMGR_QUEUE_26 /**< Queue Id for NPE B DMA Done */
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#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25 /**< Queue Id for NPE C DMA Request */
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#define IX_DMA_NPE_C_DONE_QID IX_QMGR_QUEUE_27 /**< Queue Id for NPE C DMA Done */
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/*****************************************************************************************
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* Queue assignments for Ethernet
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*
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* Note: Rx queue definitions, which include QoS traffic class definitions
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* are managed by EthDB and declared in IxEthDBQoS.h
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*****************************************************************************************/
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/**
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*
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* @def IX_ETH_ACC_RX_FRAME_ETH_Q
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*
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* @brief Eth0/Eth1 NPE Frame Receive Q.
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*
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* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
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*
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*/
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#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4)
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/**
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*
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* @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
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*
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* @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
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*
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*/
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#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q (IX_QMGR_QUEUE_27)
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/**
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*
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* @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
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*
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* @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
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*
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*/
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#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q (IX_QMGR_QUEUE_28)
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/**
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*
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* @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
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|
*
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* @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
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*
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*/
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#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q (IX_QMGR_QUEUE_26)
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|
|
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/**
|
|
*
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|
* @def IX_ETH_ACC_TX_FRAME_ENET0_Q
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|
*
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* @brief Submit frame Q for NPEB Eth 0 - Port 1
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|
*
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|
*/
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|
#define IX_ETH_ACC_TX_FRAME_ENET0_Q (IX_QMGR_QUEUE_24)
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|
|
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/**
|
|
*
|
|
* @def IX_ETH_ACC_TX_FRAME_ENET1_Q
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|
*
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|
* @brief Submit frame Q for NPEC Eth 1 - Port 2
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|
*
|
|
*/
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|
#define IX_ETH_ACC_TX_FRAME_ENET1_Q (IX_QMGR_QUEUE_25)
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|
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|
/**
|
|
*
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|
* @def IX_ETH_ACC_TX_FRAME_ENET2_Q
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|
*
|
|
* @brief Submit frame Q for NPEA Eth 2 - Port 3
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|
*
|
|
*/
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|
#define IX_ETH_ACC_TX_FRAME_ENET2_Q (IX_QMGR_QUEUE_23)
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|
|
|
/**
|
|
*
|
|
* @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
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|
*
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|
* @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
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|
*
|
|
*/
|
|
#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q (IX_QMGR_QUEUE_31)
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|
|
|
/*****************************************************************************************
|
|
* Queue assignments for Crypto
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|
*****************************************************************************************/
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|
|
|
/** Crypto Service Request Queue */
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|
#define IX_CRYPTO_ACC_CRYPTO_REQ_Q (IX_QMGR_QUEUE_29)
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|
|
|
/** Crypto Service Done Queue */
|
|
#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
|
|
|
|
/** Crypto Req Q CB tag */
|
|
#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG (0)
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|
|
|
/** Crypto Done Q CB tag */
|
|
#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG (1)
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|
|
|
/** WEP Service Request Queue */
|
|
#define IX_CRYPTO_ACC_WEP_REQ_Q (IX_QMGR_QUEUE_21)
|
|
|
|
/** WEP Service Done Queue */
|
|
#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
|
|
|
|
/** WEP Req Q CB tag */
|
|
#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG (2)
|
|
|
|
/** WEP Done Q CB tag */
|
|
#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG (3)
|
|
|
|
/** Number of queues allocate to crypto hardware accelerator services */
|
|
#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q (2)
|
|
|
|
/** Number of queues allocate to WEP NPE services */
|
|
#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q (2)
|
|
|
|
/** Number of queues allocate to CryptoAcc component */
|
|
#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)
|
|
|
|
#endif /* IxQueueAssignments_H */
|