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https://github.com/smaeul/u-boot.git
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5862eb8b85
The cpu_sun9i.h header file defined the base addresses for quite some peripherals of the Allwinner A80 CPU, even though we now only use a fraction of that. Most of the addresses are now either read from the DT, or were never used in U-Boot in the first place. Removed the ones that are not used in the whole of the U-Boot source. to make it clear that this file only contains addresses that are needed for the SPL operation. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*/
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#ifndef _SUNXI_CPU_SUN9I_H
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#define _SUNXI_CPU_SUN9I_H
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#define REGS_AHB0_BASE 0x01C00000
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#define REGS_AHB1_BASE 0x00800000
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#define REGS_AHB2_BASE 0x03000000
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#define REGS_APB0_BASE 0x06000000
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#define REGS_APB1_BASE 0x07000000
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#define REGS_RCPUS_BASE 0x08000000
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#define SUNXI_SRAM_D_BASE 0x08100000
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/* AHB0 Module */
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#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
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#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
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/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
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#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200)
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#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
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#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
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#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
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#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
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#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
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#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
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#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
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#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
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#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
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#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
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#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
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#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
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#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
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#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
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#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
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#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
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#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
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/* APB0 Module */
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#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
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#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
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#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
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/* APB1 Module */
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#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
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#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
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/* RCPUS Module */
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#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
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#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
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#ifndef __ASSEMBLY__
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void sunxi_board_init(void);
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void sunxi_reset(void);
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int sunxi_get_sid(unsigned int *sid);
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#endif
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#endif /* _SUNXI_CPU_SUN9I_H */
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