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Import cvmx-sriox-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_SRIOX_DEFS_H__
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#define __CVMX_SRIOX_DEFS_H__
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#define CVMX_SRIOX_STATUS_REG(offset) (0x00011800C8000100ull + ((offset) & 3) * 0x1000000ull)
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/**
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* cvmx_srio#_status_reg
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*
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* The SRIO field displays if the port has been configured for SRIO operation. This register
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* can be read regardless of whether the SRIO is selected or being reset. Although some other
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* registers can be accessed while the ACCESS bit is zero (see individual registers for details),
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* the majority of SRIO registers and all the SRIOMAINT registers can be used only when the
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* ACCESS bit is asserted.
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*
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* This register is reset by the coprocessor-clock reset.
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*/
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union cvmx_sriox_status_reg {
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u64 u64;
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struct cvmx_sriox_status_reg_s {
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u64 reserved_9_63 : 55;
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u64 host : 1;
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u64 spd : 4;
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u64 run_type : 2;
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u64 access : 1;
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u64 srio : 1;
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} s;
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struct cvmx_sriox_status_reg_cn63xx {
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u64 reserved_2_63 : 62;
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u64 access : 1;
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u64 srio : 1;
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} cn63xx;
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struct cvmx_sriox_status_reg_cn63xx cn63xxp1;
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struct cvmx_sriox_status_reg_cn63xx cn66xx;
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struct cvmx_sriox_status_reg_s cnf75xx;
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};
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typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t;
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#endif
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