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1d29c718b7
Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND to do cache flush operation in M-mode and S-mode. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
38 lines
920 B
C
38 lines
920 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Andes Technology Corporation
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*/
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#ifndef _ASM_ANDES_CSR_H
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#define _ASM_ANDES_CSR_H
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#include <asm/asm.h>
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#include <linux/bitops.h>
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#include <linux/const.h>
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MMISC_CTL 0x7d0
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#define CSR_UCCTLCOMMAND 0x80c
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/* mcache_ctl register */
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#define MCACHE_CTL_IC_EN BIT(0)
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#define MCACHE_CTL_DC_EN BIT(1)
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#define MCACHE_CTL_IC_ECCEN BIT(3)
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#define MCACHE_CTL_DC_ECCEN BIT(5)
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#define MCACHE_CTL_CCTL_SUEN BIT(8)
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#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
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#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
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#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
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#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
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#define MCACHE_CTL_TLB_ECCEN BIT(18)
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#define MCACHE_CTL_DC_COHEN BIT(19)
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#define MCACHE_CTL_DC_COHSTA BIT(20)
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/* mmisc_ctl register */
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#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
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#define CCTL_L1D_WBINVAL_ALL 6
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#endif /* _ASM_ANDES_CSR_H */
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