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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <linux/delay.h>
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/* AS3722-PMIC-specific early init regs */
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#define AS3722_I2C_ADDR 0x80
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#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
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#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
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#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
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#define AS3722_SDCONTROL_REG 0x4D
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#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
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#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
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#define AS3722_LDCONTROL_REG 0x4E
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#if defined(CONFIG_TARGET_VENICE2)
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#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
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#else /* TK1 or Nyan-Big */
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#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
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#endif
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#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
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#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
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#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
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#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
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#endif
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#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
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#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
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#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
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#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
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#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
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#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
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/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
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void pmic_enable_cpu_vdd(void)
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{
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debug("%s entry\n", __func__);
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#ifdef AS3722_SD1VOLTAGE_DATA
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/* Set up VDD_CORE, for boards where OTP is incorrect*/
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debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
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/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
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tegra_i2c_ll_write(AS3722_I2C_ADDR,
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AS3722_SD1VOLTAGE_DATA);
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/*
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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#endif
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debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
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/*
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* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
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* First set VDD to 1.0V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write(AS3722_I2C_ADDR,
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AS3722_SD0VOLTAGE_DATA);
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/*
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
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/*
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* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
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* First set VDD to 1.0V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write(AS3722_I2C_ADDR,
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AS3722_SD6VOLTAGE_DATA);
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/*
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
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/*
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* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
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* First set VDD to 1.2V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write(AS3722_I2C_ADDR,
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AS3722_LDO2VOLTAGE_DATA);
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/*
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
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/*
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* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
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* First set it to bypass 3.3V straight thru, then enable the regulator
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*
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* NOTE: We do this early because doing it later seems to hose the CPU
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* power rail/partition startup. Need to debug.
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*/
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tegra_i2c_ll_write(AS3722_I2C_ADDR,
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AS3722_LDO6VOLTAGE_DATA);
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/*
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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}
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