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Use proper project name in README, rst and comment.
Done in connection to commit bb922ca3eb4b ("global: Use proper project name
U-Boot (next)").
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexander Graf <graf@csgraf.de> (ppce500)
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/536af05e7061982f15b668e87f941cdabfa25392.1694157084.git.michal.simek@amd.com
138 lines
3.5 KiB
ReStructuredText
138 lines
3.5 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. (C) Copyright 2020 Xilinx, Inc.
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ZYNQMP-R5
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=========
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About this
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----------
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This document describes the information about Xilinx Zynq UltraScale+ MPSOC
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U-Boot Cortex R5 support.
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ZynqMP R5 boards
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----------------
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* zynqmp-r5 - U-Boot running on RPU Cortex-R5
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Building
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--------
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configure and build armv7 toolchain::
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$ make xilinx_zynqmp_r5_defconfig
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$ make
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Notes
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^^^^^
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Output fragment is U-Boot.
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Loading
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-------
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ZynqMP R5 U-Boot was created for supporting loading OS on RPU. There are two
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ways how to start U-Boot on R5.
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Bootgen
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^^^^^^^
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The first way is to use Xilinx FSBL (First stage
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bootloader) to load U-Boot and start it. The following bif can be used for boot
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image generation via Xilinx bootgen utility::
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the_ROM_image:
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{
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[bootloader,destination_cpu=r5-0] fsbl_rpu.elf
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[destination_cpu=r5-0]u-boot.elf
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}
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Bootgen command for building boot.bin::
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bootgen -image <bif>.bif -r -w -o i boot.bin
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U-Boot cpu command
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^^^^^^^^^^^^^^^^^^
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The second way to load U-Boot to Cortex R5 is from U-Boot running on A53 as is
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visible from the following log::
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U-Boot SPL 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
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PMUFW: v1.1
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Loading new PMUFW cfg obj (2024 bytes)
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EL Level: EL3
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Multiboot: 0
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Trying to boot from MMC2
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spl: could not initialize mmc. error: -19
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Trying to boot from MMC1
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spl_load_image_fat_os: error reading image u-boot.bin, err - -2
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NOTICE: ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000
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NOTICE: BL31: v2.2(release):v2.2-614-ged9dc512fb9c
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NOTICE: BL31: Built : 09:32:09, Mar 13 2020
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U-Boot 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
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Model: ZynqMP ZCU104 RevC
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Board: Xilinx ZynqMP
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DRAM: 2 GiB
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PMUFW: v1.1
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EL Level: EL2
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Chip ID: zu7e
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WDT: Started with servicing (60s timeout)
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NAND: 0 MiB
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MMC: mmc@ff170000: 0
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Loading Environment from FAT... *** Warning - bad CRC, using default environment
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In: serial
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Out: serial
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Err: serial
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Bootmode: LVL_SHFT_SD_MODE1
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Reset reason: SOFT
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Net:
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ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id
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eth0: ethernet@ff0e0000
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Hit any key to stop autoboot: 0
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ZynqMP> setenv autoload no
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ZynqMP> dhcp
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BOOTP broadcast 1
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DHCP client bound to address 192.168.0.167 (8 ms)
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ZynqMP> tftpboot 20000000 192.168.0.105:u-boot-r5-2.elf
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Using ethernet@ff0e0000 device
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TFTP from server 192.168.0.105; our IP address is 192.168.0.167
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Filename 'u-boot-r5-2.elf'.
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Load address: 0x20000000
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Loading: #################################################################
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#################################################################
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#################################################################
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#################################################################
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#################################################################
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#################################################################
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################
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376 KiB/s
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done
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Bytes transferred = 2075464 (1fab48 hex)
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ZynqMP> setenv autostart no
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ZynqMP> bootelf -p 20000000
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ZynqMP> cpu 4 release 10000000 lockstep
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Using TCM jump trampoline for address 0x10000000
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R5 lockstep mode
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ZynqMP>
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Then on second uart you can see U-Boot up and running on R5::
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U-Boot 2020.10-rc4-00071-g7045622cc9ba (Sep 16 2020 - 13:38:53 +0200)
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Model: Xilinx ZynqMP R5
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DRAM: 512 MiB
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MMC:
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In: serial@ff010000
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Out: serial@ff010000
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Err: serial@ff010000
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Net: No ethernet found.
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ZynqMP r5>
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Please make sure MIO pins for uart are properly configured to see output.
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