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7b7808ae6d
Move DaVinci PSC support from board/* to cpu/* where it belongs. The PSC module manages clocks and resets for all DaVinci-family SoCs, and isn't at all board-specific. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
153 lines
4.3 KiB
C
153 lines
4.3 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include "../common/misc.h"
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#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
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#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
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#define INTEGRITY_SYSCFG_OFFSET 0x7E8
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#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
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#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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davinci_errata_workarounds();
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_GPIO);
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#if !defined(CONFIG_SYS_USE_DSPLINK)
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/* Powerup the DSP */
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dsp_on();
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#endif /* CONFIG_SYS_USE_DSPLINK */
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davinci_enable_uart0();
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davinci_enable_emac();
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davinci_enable_i2c();
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lpsc_on(DAVINCI_LPSC_TIMER1);
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timer_init();
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return(0);
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}
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/* Read ethernet MAC address from Integrity data structure inside EEPROM.
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* Returns 1 if found, 0 otherwise.
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*/
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static int sffsdr_read_mac_address(uint8_t *buf)
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{
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u_int32_t value, mac[2], address;
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/* Read Integrity data structure checkword. */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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goto err;
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if (value != INTEGRITY_CHECKWORD_VALUE)
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return 0;
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/* Read SYSCFG structure offset. */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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goto err;
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address = 0x800 + (int) value; /* Address of SYSCFG structure. */
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/* Read NET CONFIG structure offset. */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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goto err;
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address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
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address += 12; /* Address of NET INTERFACE CONFIG structure. */
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/* Read NET INTERFACE CONFIG 2 structure offset. */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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goto err;
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address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
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* CONFIG 2 structure. */
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/* Read MAC address. */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
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goto err;
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buf[0] = mac[0] >> 24;
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buf[1] = mac[0] >> 16;
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buf[2] = mac[0] >> 8;
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buf[3] = mac[0];
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buf[4] = mac[1] >> 24;
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buf[5] = mac[1] >> 16;
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return 1; /* Found */
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err:
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printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
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return 0;
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}
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/* Platform dependent initialisation. */
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int misc_init_r(void)
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{
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uint8_t i2cbuf;
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uint8_t eeprom_enetaddr[6];
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/* EMIF-A CS3 configuration for FPGA. */
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REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
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dv_display_clk_infos();
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/* Configure I2C switch (PCA9543) to enable channel 0. */
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i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
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if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
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CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
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printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
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return 1;
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}
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/* Read Ethernet MAC address from EEPROM if available. */
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if (sffsdr_read_mac_address(eeprom_enetaddr))
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dv_configure_mac_address(eeprom_enetaddr);
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if (!eth_hw_init())
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printf("Ethernet init failed\n");
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return(0);
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}
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