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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
330 lines
7.7 KiB
C
330 lines
7.7 KiB
C
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
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*
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* Copyright (C) 2005 HP Labs
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* WARNING:
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*
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* As the code is right now, it expects all PIO ports A,B,C,...
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* to be evenly spaced in the memory map:
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* ATMEL_BASE_PIOA + port * sizeof at91pio_t
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* This might not necessaryly be true in future Atmel SoCs.
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* This code should be fixed to use a pointer array to the ports.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pio.h>
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int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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if (use_pullup)
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writel(1 << pin, &pio->port[port].puer);
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else
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writel(1 << pin, &pio->port[port].pudr);
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writel(mask, &pio->port[port].per);
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}
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return 0;
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}
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/*
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* mux the pin to the "GPIO" peripheral role.
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*/
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int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(mask, &pio->port[port].per);
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}
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return 0;
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}
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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#if defined(CPU_HAS_PIO3)
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writel(readl(&pio->port[port].abcdsr1) & ~mask,
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&pio->port[port].abcdsr1);
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writel(readl(&pio->port[port].abcdsr2) & ~mask,
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&pio->port[port].abcdsr2);
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#else
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writel(mask, &pio->port[port].asr);
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#endif
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writel(mask, &pio->port[port].pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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#if defined(CPU_HAS_PIO3)
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writel(readl(&pio->port[port].abcdsr1) | mask,
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&pio->port[port].abcdsr1);
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writel(readl(&pio->port[port].abcdsr2) & ~mask,
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&pio->port[port].abcdsr2);
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#else
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writel(mask, &pio->port[port].bsr);
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#endif
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writel(mask, &pio->port[port].pdr);
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}
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return 0;
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}
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#if defined(CPU_HAS_PIO3)
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/*
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* mux the pin to the "C" internal peripheral role.
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*/
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int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(readl(&pio->port[port].abcdsr1) & ~mask,
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&pio->port[port].abcdsr1);
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writel(readl(&pio->port[port].abcdsr2) | mask,
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&pio->port[port].abcdsr2);
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writel(mask, &pio->port[port].pdr);
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}
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return 0;
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}
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/*
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* mux the pin to the "D" internal peripheral role.
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*/
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int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(readl(&pio->port[port].abcdsr1) | mask,
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&pio->port[port].abcdsr1);
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writel(readl(&pio->port[port].abcdsr2) | mask,
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&pio->port[port].abcdsr2);
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writel(mask, &pio->port[port].pdr);
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}
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return 0;
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}
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#endif
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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at91_set_pio_pullup(port, pin, use_pullup);
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writel(mask, &pio->port[port].odr);
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writel(mask, &pio->port[port].per);
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}
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return 0;
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int at91_set_pio_output(unsigned port, u32 pin, int value)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].idr);
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writel(mask, &pio->port[port].pudr);
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if (value)
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writel(mask, &pio->port[port].sodr);
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else
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writel(mask, &pio->port[port].codr);
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writel(mask, &pio->port[port].oer);
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writel(mask, &pio->port[port].per);
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}
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return 0;
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}
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/*
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* enable/disable the glitch filter. mostly used with IRQ handling.
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*/
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int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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if (is_on) {
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#if defined(CPU_HAS_PIO3)
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writel(mask, &pio->port[port].ifscdr);
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#endif
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writel(mask, &pio->port[port].ifer);
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} else {
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writel(mask, &pio->port[port].ifdr);
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}
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}
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return 0;
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}
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#if defined(CPU_HAS_PIO3)
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/*
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* enable/disable the debounce filter.
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*/
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int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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if (is_on) {
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writel(mask, &pio->port[port].ifscer);
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writel(div & PIO_SCDR_DIV, &pio->port[port].scdr);
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writel(mask, &pio->port[port].ifer);
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} else {
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writel(mask, &pio->port[port].ifdr);
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}
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}
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return 0;
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}
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/*
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* enable/disable the pull-down.
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* If pull-up already enabled while calling the function, we disable it.
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*/
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int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(mask, &pio->port[port].pudr);
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if (is_on)
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writel(mask, &pio->port[port].ppder);
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else
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writel(mask, &pio->port[port].ppddr);
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}
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return 0;
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}
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/*
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* disable Schmitt trigger
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*/
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int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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writel(readl(&pio->port[port].schmitt) | mask,
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&pio->port[port].schmitt);
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}
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return 0;
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}
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#endif
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/*
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* enable/disable the multi-driver. This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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if (is_on)
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writel(mask, &pio->port[port].mder);
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else
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writel(mask, &pio->port[port].mddr);
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}
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return 0;
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}
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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int at91_set_pio_value(unsigned port, unsigned pin, int value)
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{
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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if (value)
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writel(mask, &pio->port[port].sodr);
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else
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writel(mask, &pio->port[port].codr);
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}
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return 0;
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}
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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int at91_get_pio_value(unsigned port, unsigned pin)
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{
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u32 pdsr = 0;
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
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u32 mask;
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
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mask = 1 << pin;
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pdsr = readl(&pio->port[port].pdsr) & mask;
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}
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return pdsr != 0;
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}
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