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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Author: Timur Tabi <timur@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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#define SRDS2_MAX_LANES 2
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static u32 serdes1_prtcl_map, serdes2_prtcl_map;
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static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x00] = {NONE, NONE, NONE, NONE},
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[0x01] = {NONE, NONE, NONE, NONE},
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[0x02] = {NONE, NONE, NONE, NONE},
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[0x03] = {NONE, NONE, NONE, NONE},
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[0x04] = {NONE, NONE, NONE, NONE},
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[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
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[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
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[0x09] = {PCIE1, NONE, NONE, NONE},
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[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
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[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
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[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
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};
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static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
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[0x00] = {PCIE3, PCIE3},
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[0x01] = {PCIE2, PCIE3},
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[0x02] = {SATA1, SATA2},
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[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x04] = {NONE, NONE},
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[0x06] = {SATA1, SATA2},
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[0x07] = {NONE, NONE},
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[0x09] = {PCIE3, PCIE2},
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[0x0a] = {SATA1, SATA2},
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[0x0b] = {NONE, NONE},
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[0x0d] = {PCIE3, PCIE2},
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[0x0e] = {SATA1, SATA2},
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[0x0f] = {NONE, NONE},
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[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x16] = {SATA1, SATA2},
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[0x17] = {NONE, NONE},
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[0x18] = {PCIE3, PCIE3},
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[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x1a] = {SATA1, SATA2},
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[0x1b] = {NONE, NONE},
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[0x1c] = {PCIE3, PCIE3},
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[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x1e] = {SATA1, SATA2},
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[0x1f] = {NONE, NONE},
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret = (1 << device) & serdes1_prtcl_map;
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if (ret)
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return ret;
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return (1 << device) & serdes2_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
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serdes2_prtcl_map |= (1 << lane_prtcl);
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}
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}
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