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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
133 lines
3.8 KiB
C
133 lines
3.8 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*
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* SPR test
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*
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* The test checks the contents of Special Purpose Registers (SPR) listed
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* in the spr_test_list array below.
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* Each SPR value is read using mfspr instruction, some bits are masked
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* according to the table and the resulting value is compared to the
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* corresponding table value.
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*/
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_SPR
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static struct
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{
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int number;
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char * name;
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unsigned long mask;
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unsigned long value;
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} spr_test_list [] = {
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/* Standard Special-Purpose Registers */
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{1, "XER", 0x00000000, 0x00000000},
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{8, "LR", 0x00000000, 0x00000000},
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{9, "CTR", 0x00000000, 0x00000000},
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{18, "DSISR", 0x00000000, 0x00000000},
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{19, "DAR", 0x00000000, 0x00000000},
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{22, "DEC", 0x00000000, 0x00000000},
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{26, "SRR0", 0x00000000, 0x00000000},
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{27, "SRR1", 0x00000000, 0x00000000},
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{272, "SPRG0", 0x00000000, 0x00000000},
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{273, "SPRG1", 0x00000000, 0x00000000},
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{274, "SPRG2", 0x00000000, 0x00000000},
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{275, "SPRG3", 0x00000000, 0x00000000},
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{287, "PVR", 0xFFFF0000, 0x00500000},
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/* Additional Special-Purpose Registers */
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{144, "CMPA", 0x00000000, 0x00000000},
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{145, "CMPB", 0x00000000, 0x00000000},
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{146, "CMPC", 0x00000000, 0x00000000},
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{147, "CMPD", 0x00000000, 0x00000000},
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{148, "ICR", 0xFFFFFFFF, 0x00000000},
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{149, "DER", 0x00000000, 0x00000000},
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{150, "COUNTA", 0xFFFFFFFF, 0x00000000},
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{151, "COUNTB", 0xFFFFFFFF, 0x00000000},
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{152, "CMPE", 0x00000000, 0x00000000},
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{153, "CMPF", 0x00000000, 0x00000000},
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{154, "CMPG", 0x00000000, 0x00000000},
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{155, "CMPH", 0x00000000, 0x00000000},
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{156, "LCTRL1", 0xFFFFFFFF, 0x00000000},
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{157, "LCTRL2", 0xFFFFFFFF, 0x00000000},
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{158, "ICTRL", 0xFFFFFFFF, 0x00000007},
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{159, "BAR", 0x00000000, 0x00000000},
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{630, "DPDR", 0x00000000, 0x00000000},
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{631, "DPIR", 0x00000000, 0x00000000},
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{638, "IMMR", 0xFFFF0000, CONFIG_SYS_IMMR },
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{560, "IC_CST", 0x8E380000, 0x00000000},
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{561, "IC_ADR", 0x00000000, 0x00000000},
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{562, "IC_DAT", 0x00000000, 0x00000000},
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{568, "DC_CST", 0xEF380000, 0x00000000},
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{569, "DC_ADR", 0x00000000, 0x00000000},
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{570, "DC_DAT", 0x00000000, 0x00000000},
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{784, "MI_CTR", 0xFFFFFFFF, 0x00000000},
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{786, "MI_AP", 0x00000000, 0x00000000},
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{787, "MI_EPN", 0x00000000, 0x00000000},
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{789, "MI_TWC", 0xFFFFFE02, 0x00000000},
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{790, "MI_RPN", 0x00000000, 0x00000000},
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{816, "MI_DBCAM", 0x00000000, 0x00000000},
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{817, "MI_DBRAM0", 0x00000000, 0x00000000},
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{818, "MI_DBRAM1", 0x00000000, 0x00000000},
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{792, "MD_CTR", 0xFFFFFFFF, 0x04000000},
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{793, "M_CASID", 0xFFFFFFF0, 0x00000000},
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{794, "MD_AP", 0x00000000, 0x00000000},
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{795, "MD_EPN", 0x00000000, 0x00000000},
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{796, "M_TWB", 0x00000003, 0x00000000},
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{797, "MD_TWC", 0x00000003, 0x00000000},
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{798, "MD_RPN", 0x00000000, 0x00000000},
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{799, "M_TW", 0x00000000, 0x00000000},
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{824, "MD_DBCAM", 0x00000000, 0x00000000},
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{825, "MD_DBRAM0", 0x00000000, 0x00000000},
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{826, "MD_DBRAM1", 0x00000000, 0x00000000},
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};
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static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
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int spr_post_test (int flags)
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{
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int ret = 0;
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int ic = icache_status ();
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int i;
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unsigned long code[] = {
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0x7c6002a6, /* mfspr r3,SPR */
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0x4e800020 /* blr */
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};
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unsigned long (*get_spr) (void) = (void *) code;
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if (ic)
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icache_disable ();
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for (i = 0; i < spr_test_list_size; i++) {
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int num = spr_test_list[i].number;
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/* mfspr r3,num */
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code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
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if ((get_spr () & spr_test_list[i].mask) !=
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(spr_test_list[i].value & spr_test_list[i].mask)) {
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post_log ("The value of %s special register "
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"is incorrect: 0x%08X\n",
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spr_test_list[i].name, get_spr ());
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ret = -1;
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}
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}
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if (ic)
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icache_enable ();
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */
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