mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-04 05:50:17 +00:00
6cc04547cb
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2000-2003
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*
|
|
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
|
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <clock_legacy.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/global_data.h>
|
|
|
|
#ifdef CONFIG_FSL_ESDHC_IMX
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
#endif
|
|
|
|
int get_clocks(void)
|
|
{
|
|
#ifdef CONFIG_FSL_ESDHC_IMX
|
|
#ifdef CONFIG_FSL_USDHC
|
|
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
#else
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
#endif
|
|
#else
|
|
#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
#else
|
|
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
#endif
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|