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	Add support for imx8mn architecture in order to run the NAND in fast edo mode. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
		
			
				
	
	
		
			183 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			183 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * NXP GPMI NAND flash driver (DT initialization)
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|  *
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|  * Copyright (C) 2018 Toradex
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|  * Copyright 2019 NXP
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|  *
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|  * Authors:
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|  * Stefan Agner <stefan.agner@toradex.com>
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|  *
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|  * Based on denali_dt.c
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <dm.h>
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| #include <linux/io.h>
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| #include <linux/ioport.h>
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| #include <linux/printk.h>
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| #include <clk.h>
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| 
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| #include <mxs_nand.h>
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| 
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| struct mxs_nand_dt_data {
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| 	unsigned int max_ecc_strength_supported;
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| 	int max_chain_delay; /* See the async EDO mode */
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| };
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| 
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| static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
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| 	.max_ecc_strength_supported = 40,
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| 	.max_chain_delay = 12000,
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| };
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| 
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| static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = {
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| 	.max_ecc_strength_supported = 62,
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| 	.max_chain_delay = 12000,
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| };
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| 
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| static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
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| 	.max_ecc_strength_supported = 62,
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| 	.max_chain_delay = 12000,
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| };
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| 
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| static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
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| 	.max_ecc_strength_supported = 62,
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| 	.max_chain_delay = 12000,
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| };
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| 
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| static const struct udevice_id mxs_nand_dt_ids[] = {
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| 	{
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| 		.compatible = "fsl,imx6q-gpmi-nand",
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| 		.data = (unsigned long)&mxs_nand_imx6q_data,
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| 	},
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| 	{
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| 		.compatible = "fsl,imx6qp-gpmi-nand",
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| 		.data = (unsigned long)&mxs_nand_imx6q_data,
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| 	},
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| 	{
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| 		.compatible = "fsl,imx6sx-gpmi-nand",
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| 		.data = (unsigned long)&mxs_nand_imx6sx_data,
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| 	},
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| 	{
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| 		.compatible = "fsl,imx7d-gpmi-nand",
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| 		.data = (unsigned long)&mxs_nand_imx7d_data,
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| 	},
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| 	{
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| 		.compatible = "fsl,imx8qxp-gpmi-nand",
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| 		.data = (unsigned long)&mxs_nand_imx8qxp_data,
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| 	},
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| 	{ /* sentinel */ }
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| };
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| 
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| static int mxs_nand_dt_probe(struct udevice *dev)
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| {
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| 	struct mxs_nand_info *info = dev_get_priv(dev);
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| 	const struct mxs_nand_dt_data *data;
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| 	struct resource res;
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| 	int ret;
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| 
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| 	data = (void *)dev_get_driver_data(dev);
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| 	if (data) {
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| 		info->max_ecc_strength_supported = data->max_ecc_strength_supported;
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| 		info->max_chain_delay = data->max_chain_delay;
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| 	}
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| 
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| 	info->dev = dev;
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| 
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| 	ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
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| 	if (ret)
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| 		return ret;
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| 
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| 	info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
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| 
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| 
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| 	ret = dev_read_resource_byname(dev, "bch", &res);
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| 	if (ret)
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| 		return ret;
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| 
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| 	info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
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| 
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| 	info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
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| 
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| 	if (IS_ENABLED(CONFIG_CLK) &&
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| 	    (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
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| 		/* Assigned clock already set clock */
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| 		struct clk gpmi_clk;
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| 
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| 		info->gpmi_clk = devm_clk_get(dev, "gpmi_io");
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| 
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| 		if (IS_ERR(info->gpmi_clk)) {
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| 			ret = PTR_ERR(info->gpmi_clk);
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| 			debug("Can't get gpmi io clk: %d\n", ret);
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| 			return ret;
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| 		}
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| 
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| 		ret = clk_enable(info->gpmi_clk);
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| 		if (ret < 0) {
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| 			debug("Can't enable gpmi io clk: %d\n", ret);
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| 			return ret;
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| 		}
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| 
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| 		if (IS_ENABLED(CONFIG_IMX8)) {
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| 			ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk);
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| 			if (ret < 0) {
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| 				debug("Can't get gpmi_apb clk: %d\n", ret);
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| 				return ret;
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| 			}
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| 
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| 			ret = clk_enable(&gpmi_clk);
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| 			if (ret < 0) {
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| 				debug("Can't enable gpmi_apb clk: %d\n", ret);
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| 				return ret;
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| 			}
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| 
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| 			ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk);
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| 			if (ret < 0) {
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| 				debug("Can't get gpmi_bch clk: %d\n", ret);
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| 				return ret;
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| 			}
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| 
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| 			ret = clk_enable(&gpmi_clk);
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| 			if (ret < 0) {
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| 				debug("Can't enable gpmi_bch clk: %d\n", ret);
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| 				return ret;
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| 			}
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| 		}
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| 
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| 		ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk);
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| 		if (ret < 0) {
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| 			debug("Can't get gpmi_bch_apb clk: %d\n", ret);
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| 			return ret;
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| 		}
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| 
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| 		ret = clk_enable(&gpmi_clk);
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| 		if (ret < 0) {
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| 			debug("Can't enable gpmi_bch_apb clk: %d\n", ret);
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| 			return ret;
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| 		}
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| 	}
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| 
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| 	return mxs_nand_init_ctrl(info);
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| }
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| 
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| U_BOOT_DRIVER(mxs_nand_dt) = {
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| 	.name = "mxs-nand-dt",
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| 	.id = UCLASS_MTD,
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| 	.of_match = mxs_nand_dt_ids,
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| 	.probe = mxs_nand_dt_probe,
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| 	.priv_auto	= sizeof(struct mxs_nand_info),
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| };
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| 
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| void board_nand_init(void)
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| {
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| 	struct udevice *dev;
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| 	int ret;
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| 
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| 	ret = uclass_get_device_by_driver(UCLASS_MTD,
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| 					  DM_DRIVER_GET(mxs_nand_dt),
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| 					  &dev);
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| 	if (ret && ret != -ENODEV)
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| 		pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
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| 		       ret);
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| }
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