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1965f2aa65
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
270 lines
6.2 KiB
C
270 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* NXP TJA1100 BroadRReach PHY driver
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*
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* Copyright (C) 2022 Michael Trimarchi <michael@amarulasolutions.com>
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* Copyright (C) 2022 Ariel D'Alessandro <ariel.dalessandro@collabora.com>
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* Copyright (C) 2018 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <phy.h>
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#define PHY_ID_MASK 0xfffffff0
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#define PHY_ID_TJA1100 0x0180dc40
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#define PHY_ID_TJA1101 0x0180dd00
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#define MII_ECTRL 17
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#define MII_ECTRL_LINK_CONTROL BIT(15)
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#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
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#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
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#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
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#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
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#define MII_ECTRL_CABLE_TEST BIT(5)
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#define MII_ECTRL_CONFIG_EN BIT(2)
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#define MII_ECTRL_WAKE_REQUEST BIT(0)
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#define MII_CFG1 18
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#define MII_CFG1_MASTER_SLAVE BIT(15)
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#define MII_CFG1_AUTO_OP BIT(14)
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#define MII_CFG1_SLEEP_CONFIRM BIT(6)
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#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
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#define MII_CFG1_LED_MODE_LINKUP 0
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#define MII_CFG1_LED_ENABLE BIT(3)
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#define MII_CFG2 19
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#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
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#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
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#define MII_INTSRC 21
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#define MII_INTSRC_LINK_FAIL BIT(10)
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#define MII_INTSRC_LINK_UP BIT(9)
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#define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | \
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MII_INTSRC_LINK_UP)
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#define MII_INTSRC_UV_ERR BIT(3)
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#define MII_INTSRC_TEMP_ERR BIT(1)
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#define MII_INTEN 22
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#define MII_INTEN_LINK_FAIL BIT(10)
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#define MII_INTEN_LINK_UP BIT(9)
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#define MII_INTEN_UV_ERR BIT(3)
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#define MII_INTEN_TEMP_ERR BIT(1)
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#define MII_COMMSTAT 23
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#define MII_COMMSTAT_LINK_UP BIT(15)
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#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
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#define MII_COMMSTAT_SQI_MAX 7
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#define MII_GENSTAT 24
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#define MII_GENSTAT_PLL_LOCKED BIT(14)
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#define MII_EXTSTAT 25
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#define MII_EXTSTAT_SHORT_DETECT BIT(8)
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#define MII_EXTSTAT_OPEN_DETECT BIT(7)
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#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
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#define MII_COMMCFG 27
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#define MII_COMMCFG_AUTO_OP BIT(15)
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static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
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u16 val)
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{
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return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
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}
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static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
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u16 val)
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{
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return phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
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}
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static inline int tja11xx_read(struct phy_device *phydev, int regnum)
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{
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return phy_read(phydev, MDIO_DEVAD_NONE, regnum);
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}
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static inline int tja11xx_modify(struct phy_device *phydev, int regnum,
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u16 mask, u16 set)
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{
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return phy_modify(phydev, MDIO_DEVAD_NONE, regnum, mask, set);
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}
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static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
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{
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int val;
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return read_poll_timeout(tja11xx_read, val, (val & mask) == set, 150,
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30000, phydev, reg);
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}
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static int tja11xx_modify_check(struct phy_device *phydev, u8 reg,
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u16 mask, u16 set)
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{
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int ret;
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ret = tja11xx_modify(phydev, reg, mask, set);
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if (ret)
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return ret;
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return tja11xx_check(phydev, reg, mask, set);
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}
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static int tja11xx_enable_reg_write(struct phy_device *phydev)
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{
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return tja11xx_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
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}
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static int tja11xx_enable_link_control(struct phy_device *phydev)
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{
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return tja11xx_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
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}
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static int tja11xx_wakeup(struct phy_device *phydev)
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{
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int ret;
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ret = tja11xx_read(phydev, MII_ECTRL);
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if (ret < 0)
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return ret;
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switch (ret & MII_ECTRL_POWER_MODE_MASK) {
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case MII_ECTRL_POWER_MODE_NO_CHANGE:
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break;
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case MII_ECTRL_POWER_MODE_NORMAL:
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ret = tja11xx_set_bits(phydev, MII_ECTRL,
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MII_ECTRL_WAKE_REQUEST);
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if (ret)
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return ret;
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ret = tja11xx_clear_bits(phydev, MII_ECTRL,
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MII_ECTRL_WAKE_REQUEST);
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if (ret)
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return ret;
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break;
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case MII_ECTRL_POWER_MODE_STANDBY:
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ret = tja11xx_modify_check(phydev, MII_ECTRL,
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MII_ECTRL_POWER_MODE_MASK,
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MII_ECTRL_POWER_MODE_STANDBY);
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if (ret)
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return ret;
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ret = tja11xx_modify(phydev, MII_ECTRL,
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MII_ECTRL_POWER_MODE_MASK,
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MII_ECTRL_POWER_MODE_NORMAL);
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if (ret)
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return ret;
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ret = tja11xx_modify_check(phydev, MII_GENSTAT,
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MII_GENSTAT_PLL_LOCKED,
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MII_GENSTAT_PLL_LOCKED);
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if (ret)
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return ret;
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return tja11xx_enable_link_control(phydev);
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default:
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break;
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}
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return 0;
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}
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static int tja11xx_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = tja11xx_enable_reg_write(phydev);
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if (ret)
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return ret;
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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switch (phydev->phy_id & PHY_ID_MASK) {
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case PHY_ID_TJA1100:
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ret = tja11xx_modify(phydev, MII_CFG1,
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MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
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MII_CFG1_LED_ENABLE,
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MII_CFG1_AUTO_OP |
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MII_CFG1_LED_MODE_LINKUP |
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MII_CFG1_LED_ENABLE);
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if (ret)
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return ret;
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break;
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case PHY_ID_TJA1101:
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ret = tja11xx_set_bits(phydev, MII_COMMCFG,
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MII_COMMCFG_AUTO_OP);
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if (ret)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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ret = tja11xx_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
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if (ret)
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return ret;
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ret = tja11xx_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
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MII_CFG2_SLEEP_REQUEST_TO_16MS);
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if (ret)
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return ret;
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ret = tja11xx_wakeup(phydev);
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if (ret < 0)
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return ret;
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/* ACK interrupts by reading the status register */
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ret = tja11xx_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int tja11xx_startup(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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ret = tja11xx_read(phydev, MII_CFG1);
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if (ret < 0)
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return ret;
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if (phydev->link) {
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ret = tja11xx_read(phydev, MII_COMMSTAT);
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if (ret < 0)
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return ret;
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if (!(ret & MII_COMMSTAT_LINK_UP))
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phydev->link = 0;
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}
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return 0;
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}
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U_BOOT_PHY_DRIVER(tja1100) = {
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.name = "NXP TJA1100",
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.uid = PHY_ID_TJA1100,
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.mask = PHY_ID_MASK,
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.features = PHY_BASIC_FEATURES,
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.config = &tja11xx_config_init,
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.startup = &tja11xx_startup,
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.shutdown = &genphy_shutdown,
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};
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U_BOOT_PHY_DRIVER(tja1101) = {
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.name = "NXP TJA1101",
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.uid = PHY_ID_TJA1101,
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.mask = PHY_ID_MASK,
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.features = PHY_BASIC_FEATURES,
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.config = &tja11xx_config_init,
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.startup = &tja11xx_startup,
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.shutdown = &genphy_shutdown,
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};
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