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ff476897ed
Add trivial driver for the MXS AUART IP. This is the other UART IP present in i.MX23 and i.MX28, used to drive the non-DUART ports. Signed-off-by: Marek Vasut <marex@denx.de>
130 lines
3.1 KiB
C
130 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <serial.h>
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#include <wait_bit.h>
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#define SET_REG 0x4
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#define CLR_REG 0x8
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#define AUART_CTRL0 0x00
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#define AUART_CTRL1 0x10
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#define AUART_CTRL2 0x20
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#define AUART_LINECTRL 0x30
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#define AUART_INTR 0x50
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#define AUART_DATA 0x60
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#define AUART_STAT 0x70
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#define AUART_CTRL0_SFTRST BIT(31)
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#define AUART_CTRL0_CLKGATE BIT(30)
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#define AUART_CTRL2_UARTEN BIT(0)
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#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
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#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
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#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
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#define AUART_STAT_TXFE BIT(27)
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#define AUART_STAT_TXFF BIT(25)
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#define AUART_STAT_RXFE BIT(24)
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#define AUART_CLK 24000000
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struct mxs_auart_uart_priv {
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void __iomem *base;
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};
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static int mxs_auart_uart_setbrg(struct udevice *dev, int baudrate)
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{
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struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
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u32 div;
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writel(AUART_CTRL0_CLKGATE, priv->base + AUART_CTRL0 + CLR_REG);
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writel(AUART_CTRL0_SFTRST, priv->base + AUART_CTRL0 + CLR_REG);
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writel(AUART_CTRL2_UARTEN, priv->base + AUART_CTRL2 + SET_REG);
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writel(0, priv->base + AUART_INTR);
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div = DIV_ROUND_CLOSEST(AUART_CLK * 32, baudrate);
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/* Disable FIFO, baudrate, 8N1. */
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writel(AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F) |
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AUART_LINECTRL_BAUD_DIVINT(div >> 6) |
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AUART_LINECTRL_WLEN(8),
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priv->base + AUART_LINECTRL);
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return 0;
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}
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static int mxs_auart_uart_pending(struct udevice *dev, bool input)
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{
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struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
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u32 stat = readl(priv->base + AUART_STAT);
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if (input)
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return !(stat & AUART_STAT_RXFE);
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return !!(stat & AUART_STAT_TXFE);
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}
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static int mxs_auart_uart_putc(struct udevice *dev, const char ch)
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{
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struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
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u32 stat = readl(priv->base + AUART_STAT);
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if (stat & AUART_STAT_TXFF)
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return -EAGAIN;
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writel(ch, priv->base + AUART_DATA);
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return 0;
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}
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static int mxs_auart_uart_getc(struct udevice *dev)
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{
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struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
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if (!mxs_auart_uart_pending(dev, true))
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return -EAGAIN;
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return readl(priv->base + AUART_DATA) & 0xff;
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}
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static int mxs_auart_uart_probe(struct udevice *dev)
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{
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struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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return mxs_auart_uart_setbrg(dev, CONFIG_BAUDRATE);
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}
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static const struct dm_serial_ops mxs_auart_uart_ops = {
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.putc = mxs_auart_uart_putc,
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.pending = mxs_auart_uart_pending,
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.getc = mxs_auart_uart_getc,
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.setbrg = mxs_auart_uart_setbrg,
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};
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static const struct udevice_id mxs_auart_uart_ids[] = {
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{ .compatible = "fsl,imx23-auart", },
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{ .compatible = "fsl,imx28-auart", },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(mxs_auart_serial) = {
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.name = "mxs-auart",
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.id = UCLASS_SERIAL,
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.of_match = mxs_auart_uart_ids,
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.probe = mxs_auart_uart_probe,
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.ops = &mxs_auart_uart_ops,
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.priv_auto = sizeof(struct mxs_auart_uart_priv),
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};
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