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bef9fdbed2
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
339 lines
7.9 KiB
ArmAsm
339 lines
7.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007 Michal Simek
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* (C) Copyright 2004 Atmark Techno, Inc.
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*
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* Michal SIMEK <monstr@monstr.eu>
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* Yasushi SHOJI <yashi@atmark-techno.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#define SYM_ADDR(reg, reg_add, symbol) \
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mfs r20, rpc; \
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addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \
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lwi reg, r20, symbol@GOT; \
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addk reg, reg reg_add;
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.text
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.global _start
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_start:
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mts rmsr, r0 /* disable cache */
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mfs r20, rpc
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addi r20, r20, -4
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mts rslr, r0
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mts rshr, r20
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#if defined(CONFIG_XPL_BUILD)
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addi r1, r0, CONFIG_SPL_STACK
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#else
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add r1, r0, r20
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bri 1f
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/* Force alignment for easier ASM code below */
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#define ALIGNMENT_ADDR 0x20
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.align 4
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uboot_dyn_start:
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.word __rel_dyn_start
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uboot_dyn_end:
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.word __rel_dyn_end
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uboot_sym_start:
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.word __dyn_sym_start
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1:
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addi r5, r20, 0
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add r6, r0, r0
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lwi r7, r20, ALIGNMENT_ADDR
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addi r7, r7, -CONFIG_TEXT_BASE
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add r7, r7, r5
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lwi r8, r20, ALIGNMENT_ADDR + 0x4
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addi r8, r8, -CONFIG_TEXT_BASE
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add r8, r8, r5
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lwi r9, r20, ALIGNMENT_ADDR + 0x8
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addi r9, r9, -CONFIG_TEXT_BASE
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add r9, r9, r5
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addi r10, r0, CONFIG_TEXT_BASE
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brlid r15, mb_fix_rela
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nop
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#endif
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addi r1, r1, -4 /* Decrement SP to top of memory */
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/* Call board_init_f_alloc_reserve with the current stack pointer as
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* parameter. */
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add r5, r0, r1
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brlid r15, board_init_f_alloc_reserve
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nop
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/* board_init_f_alloc_reserve returns a pointer to the allocated area
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* in r3. Set the new stack pointer below this area. */
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add r1, r0, r3
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mts rshr, r1
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addi r1, r1, -4
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/* Call board_init_f_init_reserve with the address returned by
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* board_init_f_alloc_reserve as parameter. */
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add r5, r0, r3
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brlid r15, board_init_f_init_reserve
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nop
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#if !defined(CONFIG_XPL_BUILD)
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/* Setup vectors with pre-relocation symbols */
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or r5, r0, r0
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brlid r15, __setup_exceptions
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nop
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#endif
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/*
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* Initialize global data cpuinfo with default values (cache
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* size, cache line size, etc).
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*/
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brlid r15, microblaze_early_cpuinfo_init
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nop
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/* Flush cache before enable cache */
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brlid r15, flush_cache_all
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nop
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/* enable instruction and data cache */
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mfs r12, rmsr
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ori r12, r12, 0x1a0
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mts rmsr, r12
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clear_bss:
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/* clear BSS segments */
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SYM_ADDR(r5, r0, __bss_start)
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SYM_ADDR(r4, r0, __bss_end)
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cmp r6, r5, r4
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beqi r6, 3f
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2:
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swi r0, r5, 0 /* write zero to loc */
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addi r5, r5, 4 /* increment to next loc */
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cmp r6, r5, r4 /* check if we have reach the end */
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bnei r6, 2b
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3: /* jumping to board_init */
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#ifdef CONFIG_DEBUG_UART
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brlid r15, debug_uart_init
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nop
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#endif
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#ifndef CONFIG_XPL_BUILD
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or r5, r0, r0 /* flags - empty */
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bri board_init_f
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#else
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bri board_init_r
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#endif
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1: bri 1b
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#ifndef CONFIG_XPL_BUILD
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.text
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.ent __setup_exceptions
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.align 2
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/*
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* Set up reset, interrupt, user exception and hardware exception vectors.
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*
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* Parameters:
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* r5 - relocation offset (zero when setting up vectors before
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* relocation, and gd->reloc_off when setting up vectors after
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* relocation)
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* - the relocation offset is added to the _exception_handler,
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* _interrupt_handler and _hw_exception_handler symbols to reflect the
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* post-relocation memory addresses
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*
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* Reserve registers:
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* r10: Stores little/big endian offset for vectors
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* r2: Stores imm opcode
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* r3: Stores brai opcode
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* r4: Stores the vector base address
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*/
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__setup_exceptions:
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addik r1, r1, -32
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swi r2, r1, 4
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swi r3, r1, 8
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swi r4, r1, 12
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swi r6, r1, 16
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swi r7, r1, 20
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swi r8, r1, 24
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swi r10, r1, 28
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/* Find-out if u-boot is running on BIG/LITTLE endian platform
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* There are some steps which is necessary to keep in mind:
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* 1. Setup offset value to r6
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* 2. Store word offset value to address 0x0
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* 3. Load just byte from address 0x0
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* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
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* value that's why is on address 0x0
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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sw r6, r1, r0
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lbu r10, r1, r0
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
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addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
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addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
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/* Store the vector base address in r4 */
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addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
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/* reset address */
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swi r2, r4, 0x0 /* reset address - imm opcode */
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swi r3, r4, 0x4 /* reset address - brai opcode */
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SYM_ADDR(r6, r0, _start)
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/* Intentionally keep reset vector back to origin u-boot location */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x2
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sh r7, r4, r8
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rsubi r8, r10, 0x6
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sh r6, r4, r8
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#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
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/* user_vector_exception */
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swi r2, r4, 0x8 /* user vector exception - imm opcode */
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swi r3, r4, 0xC /* user vector exception - brai opcode */
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SYM_ADDR(r6, r5, _exception_handler)
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sw r6, r1, r0
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/*
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* BIG ENDIAN memory map for user exception
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* 0x8: 0xB000XXXX
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* 0xC: 0xB808XXXX
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*
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* then it is necessary to count address for storing the most significant
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* 16bits from _exception_handler address and copy it to
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* 0xa address. Big endian use offset in r10=0 that's why is it just
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* 0xa address. The same is done for the least significant 16 bits
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* for 0xe address.
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*
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* LITTLE ENDIAN memory map for user exception
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* 0x8: 0xXXXX00B0
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* 0xC: 0xXXXX08B8
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*
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* Offset is for little endian setup to 0x2. rsubi instruction decrease
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* address value to ensure that points to proper place which is
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* 0x8 for the most significant 16 bits and
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* 0xC for the least significant 16 bits
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*/
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r4, r8
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rsubi r8, r10, 0xe
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sh r6, r4, r8
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#endif
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/* interrupt_handler */
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swi r2, r4, 0x10 /* interrupt - imm opcode */
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swi r3, r4, 0x14 /* interrupt - brai opcode */
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SYM_ADDR(r6, r5, _interrupt_handler)
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r4, r8
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rsubi r8, r10, 0x16
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sh r6, r4, r8
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/* hardware exception */
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swi r2, r4, 0x20 /* hardware exception - imm opcode */
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swi r3, r4, 0x24 /* hardware exception - brai opcode */
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SYM_ADDR(r6, r5, _hw_exception_handler)
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r4, r8
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rsubi r8, r10, 0x26
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sh r6, r4, r8
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lwi r10, r1, 28
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lwi r8, r1, 24
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lwi r7, r1, 20
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lwi r6, r1, 16
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lwi r4, r1, 12
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lwi r3, r1, 8
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lwi r2, r1, 4
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addik r1, r1, 32
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rtsd r15, 8
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or r0, r0, r0
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.end __setup_exceptions
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/*
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* Relocate u-boot
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*/
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.text
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.global relocate_code
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.ent relocate_code
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.align 2
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relocate_code:
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/*
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* r5 - start_addr_sp
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* r6 - new_gd
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* r7 - reloc_addr
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*/
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addi r1, r5, 0 /* Start to use new SP */
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mts rshr, r1
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addi r31, r6, 0 /* Start to use new GD */
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/* Relocate text and data - r12 temp value */
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SYM_ADDR(r21, r0, _start)
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SYM_ADDR(r22, r0, _end) /* Include BSS too */
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addi r22, r22, -4
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rsub r6, r21, r22
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or r5, r0, r0
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1: lw r12, r21, r5 /* Load u-boot data */
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sw r12, r7, r5 /* Write zero to loc */
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cmp r12, r5, r6 /* Check if we have reach the end */
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bneid r12, 1b
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addi r5, r5, 4 /* Increment to next loc - relocate code */
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/* R23 points to the base address. */
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rsub r23, r21, r7 /* keep - this is already here gd->reloc_off */
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/* Setup vectors with post-relocation symbols */
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add r5, r0, r23 /* load gd->reloc_off to r5 */
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brlid r15, __setup_exceptions
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nop
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/* reloc_offset is current location */
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SYM_ADDR(r10, r0, _start)
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/* r5 new address where I should copy code */
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add r5, r0, r7 /* Move reloc addr to r5 */
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/* Verbose message */
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addi r6, r0, 0
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SYM_ADDR(r7, r0, __rel_dyn_start)
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rsub r7, r10, r7
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add r7, r7, r5
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SYM_ADDR(r8, r0, __rel_dyn_end)
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rsub r8, r10, r8
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add r8, r8, r5
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SYM_ADDR(r9, r0, __dyn_sym_start)
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rsub r9, r10, r9
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add r9, r9, r5
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brlid r15, mb_fix_rela
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nop
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/* end of code which does relocation */
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/* Flush caches to ensure consistency */
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brlid r15, flush_cache_all
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nop
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2: addi r5, r31, 0 /* gd is initialized in board_r.c */
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SYM_ADDR(r6, r0, _start)
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SYM_ADDR(r12, r23, board_init_r)
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bra r12 /* Jump to relocated code */
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.end relocate_code
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#endif
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