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b4256b5dca
Import Qualcomm QMP phy related header files from Linux v6.11-rc7, limit to headers needed to setup QMP v2 to v6 UFS PHYs. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
112 lines
4.7 KiB
C
112 lines
4.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_
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#define QCOM_PHY_QMP_QSERDES_COM_V3_H_
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/* Only for QMP V3 PHY - QSERDES COM registers */
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#define QSERDES_V3_COM_ATB_SEL1 0x000
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#define QSERDES_V3_COM_ATB_SEL2 0x004
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#define QSERDES_V3_COM_FREQ_UPDATE 0x008
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#define QSERDES_V3_COM_BG_TIMER 0x00c
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#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
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#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
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#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
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#define QSERDES_V3_COM_SSC_PER1 0x01c
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#define QSERDES_V3_COM_SSC_PER2 0x020
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#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
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#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
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#define QSERDES_V3_COM_POST_DIV 0x02c
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#define QSERDES_V3_COM_POST_DIV_MUX 0x030
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#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
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#define QSERDES_V3_COM_CLK_ENABLE1 0x038
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#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
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#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
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#define QSERDES_V3_COM_PLL_EN 0x044
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#define QSERDES_V3_COM_PLL_IVCO 0x048
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#define QSERDES_V3_COM_CMN_IETRIM 0x04c
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#define QSERDES_V3_COM_CMN_IPTRIM 0x050
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#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054
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#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058
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#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
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#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
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#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
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#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
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#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
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#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
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#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
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#define QSERDES_V3_COM_PLL_CNTRL 0x078
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#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c
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#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
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#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084
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#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
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#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
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#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
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#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
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#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
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#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
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#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
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#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
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#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
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#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
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#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
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#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
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#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
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#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
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#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
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#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
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#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
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#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
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#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
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#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4
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#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
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#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
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#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
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#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
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#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8
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#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
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#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
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#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
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#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
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#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
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#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
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#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
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#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
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#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c
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#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110
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#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114
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#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118
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#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
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#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
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#define QSERDES_V3_COM_CMN_STATUS 0x124
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#define QSERDES_V3_COM_RESET_SM_STATUS 0x128
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#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c
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#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130
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#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134
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#define QSERDES_V3_COM_CLK_SELECT 0x138
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#define QSERDES_V3_COM_HSCLK_SEL 0x13c
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#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140
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#define QSERDES_V3_COM_PLL_ANALOG 0x144
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#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
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#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
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#define QSERDES_V3_COM_SW_RESET 0x150
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#define QSERDES_V3_COM_CORE_CLK_EN 0x154
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#define QSERDES_V3_COM_C_READY_STATUS 0x158
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#define QSERDES_V3_COM_CMN_CONFIG 0x15c
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#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160
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#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
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#define QSERDES_V3_COM_DEBUG_BUS0 0x168
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#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
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#define QSERDES_V3_COM_DEBUG_BUS2 0x170
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#define QSERDES_V3_COM_DEBUG_BUS3 0x174
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#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
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#define QSERDES_V3_COM_CMN_MISC1 0x17c
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#define QSERDES_V3_COM_CMN_MISC2 0x180
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#define QSERDES_V3_COM_CMN_MODE 0x184
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#define QSERDES_V3_COM_CMN_VREG_SEL 0x188
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#endif
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