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https://github.com/smaeul/u-boot.git
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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
159 lines
3.0 KiB
C
159 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <asm/arch/regs.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <linux/bitops.h>
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#include <linux/sizes.h>
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#include <linux/delay.h>
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#include <ram.h>
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#include <reset.h>
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#include "starfive_ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct starfive_ddr_priv {
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struct udevice *dev;
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struct ram_info info;
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void __iomem *ctrlreg;
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void __iomem *phyreg;
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struct reset_ctl_bulk rst;
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struct clk clk;
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u32 fre;
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};
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static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
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{
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enum ddr_size_t size;
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switch (priv->info.size) {
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case SZ_2G:
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size = DDR_SIZE_2G;
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break;
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case SZ_4G:
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size = DDR_SIZE_4G;
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break;
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case 0x200000000:
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size = DDR_SIZE_8G;
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break;
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case 0x400000000:
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default:
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pr_err("unsupport size %lx\n", priv->info.size);
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return -EINVAL;
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}
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ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
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ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
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ddr_phy_start(priv->phyreg, size);
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DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
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ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
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priv->phyreg, size);
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return 0;
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}
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static int starfive_ddr_probe(struct udevice *dev)
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{
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struct starfive_ddr_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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u64 rate;
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int ret;
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priv->info.base = gd->ram_base;
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priv->info.size = gd->ram_size;
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priv->dev = dev;
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->ctrlreg = (void __iomem *)addr;
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->phyreg = (void __iomem *)addr;
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ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
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if (ret)
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return ret;
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switch (priv->fre) {
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case 2133:
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rate = 1066000000;
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break;
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case 2800:
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rate = 1400000000;
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break;
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default:
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pr_err("Unknown DDR frequency %d\n", priv->fre);
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return -EINVAL;
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};
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ret = reset_get_bulk(dev, &priv->rst);
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if (ret)
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return ret;
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ret = reset_deassert_bulk(&priv->rst);
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if (ret < 0)
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return ret;
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret)
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goto err_free_reset;
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ret = clk_set_rate(&priv->clk, rate);
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if (ret < 0)
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goto err_free_reset;
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ret = starfive_ddr_setup(dev, priv);
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printf("DDR version: dc2e84f0.\n");
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return ret;
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err_free_reset:
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reset_release_bulk(&priv->rst);
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return ret;
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}
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static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
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{
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struct starfive_ddr_priv *priv = dev_get_priv(dev);
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*info = priv->info;
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return 0;
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}
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static struct ram_ops starfive_ddr_ops = {
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.get_info = starfive_ddr_get_info,
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};
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static const struct udevice_id starfive_ddr_ids[] = {
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{ .compatible = "starfive,jh7110-dmc" },
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{ }
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};
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U_BOOT_DRIVER(starfive_ddr) = {
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.name = "starfive_ddr",
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.id = UCLASS_RAM,
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.of_match = starfive_ddr_ids,
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.ops = &starfive_ddr_ops,
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.probe = starfive_ddr_probe,
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.priv_auto = sizeof(struct starfive_ddr_priv),
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};
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