mirror of
https://github.com/smaeul/u-boot.git
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123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
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#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0
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#define GCC_BLSP1_BCR 1
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#define GCC_BLSP1_QUP1_BCR 2
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#define GCC_BLSP1_QUP2_BCR 3
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#define GCC_BLSP1_QUP3_BCR 4
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#define GCC_BLSP1_UART1_BCR 5
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#define GCC_BLSP1_UART2_BCR 6
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#define GCC_BOOT_ROM_BCR 7
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#define GCC_BTSS_BCR 8
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#define GCC_CMN_BLK_BCR 9
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#define GCC_CMN_LDO_BCR 10
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#define GCC_CE_BCR 11
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#define GCC_CRYPTO_BCR 12
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#define GCC_DCC_BCR 13
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#define GCC_DCD_BCR 14
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#define GCC_DDRSS_BCR 15
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#define GCC_EDPD_BCR 16
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#define GCC_GEPHY_BCR 17
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#define GCC_GEPHY_MDC_SW_ARES 18
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#define GCC_GEPHY_DSP_HW_ARES 19
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#define GCC_GEPHY_RX_ARES 20
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#define GCC_GEPHY_TX_ARES 21
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#define GCC_GMAC0_BCR 22
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#define GCC_GMAC0_CFG_ARES 23
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#define GCC_GMAC0_SYS_ARES 24
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#define GCC_GMAC1_BCR 25
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#define GCC_GMAC1_CFG_ARES 26
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#define GCC_GMAC1_SYS_ARES 27
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#define GCC_IMEM_BCR 28
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#define GCC_LPASS_BCR 29
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#define GCC_MDIO0_BCR 30
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#define GCC_MDIO1_BCR 31
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#define GCC_MPM_BCR 32
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#define GCC_PCIE0_BCR 33
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#define GCC_PCIE0_LINK_DOWN_BCR 34
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#define GCC_PCIE0_PHY_BCR 35
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#define GCC_PCIE0PHY_PHY_BCR 36
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#define GCC_PCIE0_PIPE_ARES 37
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#define GCC_PCIE0_SLEEP_ARES 38
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#define GCC_PCIE0_CORE_STICKY_ARES 39
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#define GCC_PCIE0_AXI_MASTER_ARES 40
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#define GCC_PCIE0_AXI_SLAVE_ARES 41
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#define GCC_PCIE0_AHB_ARES 42
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#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43
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#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44
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#define GCC_PCIE1_BCR 45
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#define GCC_PCIE1_LINK_DOWN_BCR 46
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#define GCC_PCIE1_PHY_BCR 47
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#define GCC_PCIE1PHY_PHY_BCR 48
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#define GCC_PCIE1_PIPE_ARES 49
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#define GCC_PCIE1_SLEEP_ARES 50
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#define GCC_PCIE1_CORE_STICKY_ARES 51
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#define GCC_PCIE1_AXI_MASTER_ARES 52
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#define GCC_PCIE1_AXI_SLAVE_ARES 53
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#define GCC_PCIE1_AHB_ARES 54
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#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55
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#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56
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#define GCC_PCNOC_BCR 57
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#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
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#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
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#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
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#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
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#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
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#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
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#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
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#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
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#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
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#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
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#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68
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#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69
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#define GCC_PRNG_BCR 70
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#define GCC_Q6SS_DBG_ARES 71
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#define GCC_Q6_AHB_S_ARES 72
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#define GCC_Q6_AHB_ARES 73
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#define GCC_Q6_AXIM2_ARES 74
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#define GCC_Q6_AXIM_ARES 75
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#define GCC_Q6_AXIS_ARES 76
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#define GCC_QDSS_BCR 77
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#define GCC_QPIC_BCR 78
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#define GCC_QUSB2_0_PHY_BCR 79
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#define GCC_SDCC1_BCR 80
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#define GCC_SEC_CTRL_BCR 81
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#define GCC_SPDM_BCR 82
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#define GCC_SYSTEM_NOC_BCR 83
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#define GCC_TCSR_BCR 84
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#define GCC_TLMM_BCR 85
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#define GCC_UBI0_AXI_ARES 86
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#define GCC_UBI0_AHB_ARES 87
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#define GCC_UBI0_NC_AXI_ARES 88
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#define GCC_UBI0_DBG_ARES 89
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#define GCC_UBI0_UTCM_ARES 90
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#define GCC_UBI0_CORE_ARES 91
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#define GCC_UBI32_BCR 92
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#define GCC_UNIPHY_BCR 93
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#define GCC_UNIPHY_AHB_ARES 94
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#define GCC_UNIPHY_SYS_ARES 95
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#define GCC_UNIPHY_RX_ARES 96
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#define GCC_UNIPHY_TX_ARES 97
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#define GCC_USB0_BCR 98
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#define GCC_USB0_PHY_BCR 99
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#define GCC_WCSS_BCR 100
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#define GCC_WCSS_DBG_ARES 101
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#define GCC_WCSS_ECAHB_ARES 102
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#define GCC_WCSS_ACMT_ARES 103
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#define GCC_WCSS_DBG_BDG_ARES 104
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#define GCC_WCSS_AHB_S_ARES 105
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#define GCC_WCSS_AXI_M_ARES 106
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#define GCC_WCSS_AXI_S_ARES 107
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#define GCC_WCSS_Q6_BCR 108
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#define GCC_WCSSAON_RESET 109
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#define GCC_UNIPHY_SOFT_RESET 110
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#define GCC_GEPHY_MISC_ARES 111
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#endif
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