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https://github.com/smaeul/u-boot.git
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bcc51c1512
As the sLD3 Boot ROM has a complex page table, it is difficult to set up the debug UART with enabling it. It will be much easier to initialize the UART port after switching over to the straight-mapped page table. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
146 lines
4.0 KiB
ArmAsm
146 lines
4.0 KiB
ArmAsm
/*
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <linux/sizes.h>
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#include <asm/system.h>
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ENTRY(lowlevel_init)
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mov r8, lr @ persevere link reg across call
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/*
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* The UniPhier Boot ROM loads SPL code to the L2 cache.
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* But CPUs can only do instruction fetch now because start.S has
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* cleared C and M bits.
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* First we need to turn on MMU and Dcache again to get back
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* data access to L2.
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*/
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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bl setup_init_ram @ RAM area for stack and page table
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/*
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* Now we are using the page table embedded in the Boot ROM.
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* It is not handy since it is not a straight mapped table for sLD3.
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* Also, the access to the external bus is prohibited. What we need
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* to do next is to create a page table and switch over to it.
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*/
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bl create_page_table
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bl __v7_flush_dcache_all
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/* Disable MMU and Dcache before switching Page Table */
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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bl enable_mmu
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#ifdef CONFIG_DEBUG_LL
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bl debug_ll_init
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#endif
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mov lr, r8 @ restore link
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mov pc, lr @ back to my caller
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ENDPROC(lowlevel_init)
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ENTRY(enable_mmu)
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mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
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bic r0, r0, #0x37
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orr r0, r0, #0x20 @ disable TTBR1
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mcr p15, 0, r0, c2, c0, 2
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orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
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mcr p15, 0, r0, c2, c0, 0 @ TTBR0
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mov r0, #-1 @ manager for all domains (No permission check)
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mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
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dsb
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isb
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/*
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* MMU on:
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* TLBs was already invalidated in "../start.S"
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* So, we don't need to invalidate it here.
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*/
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr
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ENDPROC(enable_mmu)
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/*
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* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
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* It is large enough for tmp RAM.
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*/
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#define BOOT_RAM_SIZE (SZ_32K)
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#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
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#define BOOT_RAM_WAYS (0x00000100) @ way 8
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#define SSCO_BASE 0x506c0000
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#define SSCOPE 0x244
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#define SSCOQM 0x248
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#define SSCOQAD 0x24c
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#define SSCOQSZ 0x250
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#define SSCOQWN 0x258
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#define SSCOPPQSEF 0x25c
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#define SSCOLPQS 0x260
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ENTRY(setup_init_ram)
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ldr r1, = SSCO_BASE
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mrc p15, 0, r0, c2, c0, 0 @ TTBR0
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ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
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bfc r0, #0, #20
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cmp r0, #0x50000000 @ is sLD3 page table?
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biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
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/* Touch to zero for the boot way */
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0: ldr r0, = 0x00408006 @ touch to zero with address range
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str r0, [r1, #SSCOQM]
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ldr r0, = BOOT_RAM_BASE
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str r0, [r1, #SSCOQAD]
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ldr r0, = BOOT_RAM_SIZE
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str r0, [r1, #SSCOQSZ]
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ldr r0, = BOOT_RAM_WAYS
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str r0, [r1, #SSCOQWN]
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ldr r0, [r1, #SSCOPPQSEF]
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cmp r0, #0 @ check if the command is successfully set
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bne 0b @ try again if an error occurs
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1: ldr r0, [r1, #SSCOLPQS]
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cmp r0, #0x4
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bne 1b @ wait until the operation is completed
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str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
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mov pc, lr
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ENDPROC(setup_init_ram)
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#define DEVICE 0x00002002 /* Non-shareable Device */
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#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
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ENTRY(create_page_table)
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ldr r0, = DEVICE
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ldr r1, = BOOT_RAM_BASE
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mov r12, r1 @ r12 is preserved during D-cache flush
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0: str r0, [r1], #4 @ specify all the sections as Device
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adds r0, r0, #0x00100000
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bcc 0b
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ldr r0, = NORMAL
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str r0, [r12] @ mark the first section as Normal
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add r0, r0, #0x00100000
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str r0, [r12, #4] @ mark the second section as Normal
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mov pc, lr
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ENDPROC(create_page_table)
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