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f4d9bd06f7
The driver is actually for the Designware DWC2 controller. This patch renames the local header files to dwc2_*h and adjusts the sources to use the new names. Signed-off-by: Marek Vasut <marex@denx.de>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/*
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* Copyright 2015 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sysmap.h>
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#include "dwc2_udc_otg_priv.h"
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#include "bcm_udc_otg.h"
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void otg_phy_init(struct dwc2_udc *dev)
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{
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/* set Phy to driving mode */
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wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
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HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
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udelay(100);
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/* clear Soft Disconnect */
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wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
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HSOTG_DCTL_SFTDISCON_MASK);
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/* invoke Reset (active low) */
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wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
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HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
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/* Reset needs to be asserted for 2ms */
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udelay(2000);
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/* release Reset */
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wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
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HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
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HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
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}
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void otg_phy_off(struct dwc2_udc *dev)
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{
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/* Soft Disconnect */
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wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
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HSOTG_DCTL_SFTDISCON_MASK,
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HSOTG_DCTL_SFTDISCON_MASK);
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/* set Phy to non-driving (reset) mode */
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wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
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HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
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HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
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}
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