smaeul-u-boot

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History

David Wu 2e4ce50d1a rockchip: clk: Add rv1108 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

2017-10-01 00:33:29 +02:00

clk

ARM: dts: dra7xx: sync DT with latest Linux

2016-12-04 13:54:51 -05:00

clock

rockchip: clk: Add rv1108 SARADC clock support

2017-10-01 00:33:29 +02:00

comphy

phy: marvell: cp110: add 5G XFI mode

2017-05-09 13:38:18 +02:00

dma

…