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ed48490f8d
Previous u-boot code changed the default bch setting behavior and caused backward compatible issue. This fix choose the legacy bch geometry back again as the default option. If the minimum ecc strength that NAND chips required need to be chosen, it can be enabled by either adding DT flag "fsl,use-minimum-ecc" or CONFIG_NAND_MXS_USE_MINIMUM_ECC in configs. The unused flag "fsl,legacy-bch-geometry" get removed. Fixes: 51cdf83eea (mtd: gpmi: provide the option to use legacy bch geometry) Fixes: 616f03daba (mtd: gpmi: change the BCH layout setting for large oob NAND) Tested-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
103 lines
3.0 KiB
C
103 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* NXP GPMI NAND flash driver
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*
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* Copyright (C) 2018 Toradex
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* Authors:
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* Stefan Agner <stefan.agner@toradex.com>
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*/
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <asm/cache.h>
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#include <nand.h>
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#include <asm/mach-imx/dma.h>
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/**
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* @gf_len: The length of Galois Field. (e.g., 13 or 14)
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* @ecc_strength: A number that describes the strength of the ECC
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* algorithm.
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* @ecc_chunk0_size: The size, in bytes, of a first ECC chunk.
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* @ecc_chunkn_size: The size, in bytes, of a single ECC chunk after
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* the first chunk in the page.
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* @ecc_chunk_count: The number of ECC chunks in the page,
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* @block_mark_byte_offset: The byte offset in the ECC-based page view at
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* which the underlying physical block mark appears.
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* @block_mark_bit_offset: The bit offset into the ECC-based page view at
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* which the underlying physical block mark appears.
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* @ecc_for_meta: The flag to indicate if there is a dedicate ecc
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* for meta.
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*/
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struct bch_geometry {
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unsigned int gf_len;
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unsigned int ecc_strength;
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unsigned int ecc_chunk0_size;
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unsigned int ecc_chunkn_size;
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unsigned int ecc_chunk_count;
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unsigned int block_mark_byte_offset;
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unsigned int block_mark_bit_offset;
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unsigned int ecc_for_meta; /* ECC for meta data */
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};
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struct mxs_nand_info {
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struct nand_chip chip;
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struct udevice *dev;
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unsigned int max_ecc_strength_supported;
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bool use_minimum_ecc;
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int cur_chip;
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uint32_t cmd_queue_len;
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uint32_t data_buf_size;
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struct bch_geometry bch_geometry;
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uint8_t *cmd_buf;
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uint8_t *data_buf;
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uint8_t *oob_buf;
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uint8_t marking_block_bad;
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uint8_t raw_oob_mode;
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struct mxs_gpmi_regs *gpmi_regs;
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struct mxs_bch_regs *bch_regs;
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/* Functions with altered behaviour */
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int (*hooked_read_oob)(struct mtd_info *mtd,
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loff_t from, struct mtd_oob_ops *ops);
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int (*hooked_write_oob)(struct mtd_info *mtd,
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loff_t to, struct mtd_oob_ops *ops);
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int (*hooked_block_markbad)(struct mtd_info *mtd,
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loff_t ofs);
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/* DMA descriptors */
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struct mxs_dma_desc **desc;
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uint32_t desc_index;
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/* Hardware BCH interface and randomizer */
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u32 en_randomizer;
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u32 writesize;
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u32 oobsize;
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u32 bch_flash0layout0;
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u32 bch_flash0layout1;
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};
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struct mxs_nand_layout {
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u32 nblocks;
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u32 meta_size;
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u32 data0_size;
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u32 ecc0;
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u32 datan_size;
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u32 eccn;
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u32 gf_len;
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};
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int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
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int mxs_nand_init_spl(struct nand_chip *nand);
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int mxs_nand_setup_ecc(struct mtd_info *mtd);
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void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd);
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void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd);
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void mxs_nand_mode_normal(struct mtd_info *mtd);
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u32 mxs_nand_mark_byte_offset(struct mtd_info *mtd);
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u32 mxs_nand_mark_bit_offset(struct mtd_info *mtd);
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void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l);
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