Marek Vasut 3b44f55c3b ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 ...

Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>

2015-08-08 14:14:22 +02:00

..

altera

ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1

2015-08-08 14:14:22 +02:00

fsl

drivers/ddr/fsl: Adjust bstopre value

2015-08-03 12:06:38 -07:00

marvell

arm: mvebu: a38x: Use correct PEX register access macros

2015-07-23 10:39:25 +02:00