mirror of
https://github.com/smaeul/u-boot.git
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3b4ee40f20
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2021 Intel Corporation
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*/
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#ifndef _SOCFPGA_MISC_H_
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#define _SOCFPGA_MISC_H_
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#include <asm/sections.h>
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void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
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struct bsel {
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const char *mode;
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const char *name;
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};
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extern struct bsel bsel_str[];
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#ifdef CONFIG_FPGA
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void socfpga_fpga_add(void *fpga_desc);
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#else
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static inline void socfpga_fpga_add(void *fpga_desc) {}
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#endif
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#ifdef CONFIG_TARGET_SOCFPGA_GEN5
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void socfpga_sdram_remap_zero(void);
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static inline bool socfpga_is_booting_from_fpga(void)
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{
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if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
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(__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
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return true;
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return false;
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}
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#endif
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#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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void socfpga_init_security_policies(void);
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void socfpga_sdram_remap_zero(void);
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#endif
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#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
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defined(CONFIG_TARGET_SOCFPGA_AGILEX)
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int is_fpga_config_ready(void);
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#endif
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void do_bridge_reset(int enable, unsigned int mask);
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bool is_regular_boot_valid(void);
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void set_regular_boot(unsigned int status);
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void socfpga_pl310_clear(void);
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void socfpga_get_managers_addr(void);
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int qspi_flash_software_reset(void);
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#endif /* _SOCFPGA_MISC_H_ */
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