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914a84e6ee
Add MMU memory mapping table for Stratix SoC. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region socfpga_stratix10_mem_map[] = {
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{
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/* MEM 2GB*/
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* FPGA 1.5GB */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x60000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* DEVICE 142MB */
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.virt = 0xF7000000UL,
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.phys = 0xF7000000UL,
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.size = 0x08E00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* OCRAM 1MB but available 256KB */
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.virt = 0xFFE00000UL,
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.phys = 0xFFE00000UL,
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.size = 0x00100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* DEVICE 32KB */
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.virt = 0xFFFC0000UL,
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.phys = 0xFFFC0000UL,
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.size = 0x00008000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* MEM 124GB */
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.virt = 0x0100000000UL,
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.phys = 0x0100000000UL,
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.size = 0x1F00000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* DEVICE 4GB */
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.virt = 0x2000000000UL,
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.phys = 0x2000000000UL,
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.size = 0x0100000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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/* List terminator */
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},
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};
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struct mm_region *mem_map = socfpga_stratix10_mem_map;
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