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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <reset-uclass.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dm/lists.h>
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/*
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* Each reg has 16 bits reset signal for devices
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* Note: Not including rk2818 and older SoCs
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*/
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#define ROCKCHIP_RESET_NUM_IN_REG 16
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struct rockchip_reset_priv {
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void __iomem *base;
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/* Rockchip reset reg locate at cru controller */
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u32 reset_reg_offset;
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/* Rockchip reset reg number */
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u32 reset_reg_num;
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};
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static int rockchip_reset_request(struct reset_ctl *reset_ctl)
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{
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struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
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reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
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if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
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return -EINVAL;
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return 0;
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}
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static int rockchip_reset_free(struct reset_ctl *reset_ctl)
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{
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
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reset_ctl->dev, reset_ctl->id);
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return 0;
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}
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static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
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{
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struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
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int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
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reset_ctl, reset_ctl->dev, reset_ctl->id,
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priv->base + (bank * 4));
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rk_setreg(priv->base + (bank * 4), BIT(offset));
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return 0;
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}
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static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
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{
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struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
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int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
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reset_ctl, reset_ctl->dev, reset_ctl->id,
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priv->base + (bank * 4));
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rk_clrreg(priv->base + (bank * 4), BIT(offset));
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return 0;
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}
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struct reset_ops rockchip_reset_ops = {
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.request = rockchip_reset_request,
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.rfree = rockchip_reset_free,
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.rst_assert = rockchip_reset_assert,
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.rst_deassert = rockchip_reset_deassert,
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};
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static int rockchip_reset_probe(struct udevice *dev)
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{
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struct rockchip_reset_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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fdt_size_t size;
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addr = dev_read_addr_size(dev, "reg", &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
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return -EINVAL;
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addr += priv->reset_reg_offset;
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priv->base = ioremap(addr, size);
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debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
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priv->base, priv->reset_reg_offset, priv->reset_reg_num);
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return 0;
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}
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int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
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{
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struct udevice *rst_dev;
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struct rockchip_reset_priv *priv;
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int ret;
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ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
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dev_ofnode(pdev), &rst_dev);
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if (ret) {
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debug("Warning: No rockchip reset driver: ret=%d\n", ret);
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return ret;
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}
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priv = malloc(sizeof(struct rockchip_reset_priv));
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priv->reset_reg_offset = reg_offset;
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priv->reset_reg_num = reg_number;
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rst_dev->priv = priv;
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return 0;
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}
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U_BOOT_DRIVER(rockchip_reset) = {
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.name = "rockchip_reset",
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.id = UCLASS_RESET,
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.probe = rockchip_reset_probe,
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.ops = &rockchip_reset_ops,
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.priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
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};
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